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This style sheet is intended only as an overview and does not cover all aspects of the APA style. For more information, see the Publication Manual of the American Psychological Association or a style guide to writing research papers. The Writing Center has these and other resources on hand, and Writing Center tutors can help you to use them. The APA style refers to Examples | Rn Cover the method of writing research papers recommended by the American Psychological Association. The APA style is used in the social sciences and Style is governed by two basic ideas. The first is De Imagem Para Storyboard that a scientific paper attempts to show something that has already been proven true, so it calls for the past or present perfect tense when you cite the work of others. Second, the year of publication is important, so you need to feature it immediately after any named source in the text. Smyth (1972) found that children often studied while watching television.
Williams and Maier (1994) have defined a new theory of Chart, cognition. Use the present tense for generalizations and personal comments. Use the past or present perfect tenses only to introduce the work of cited sources. Evidence of the rise of the heroin use exists for 132 Best Maths Prep To Three Images Value every age group, even children. Burroughs and Bruce (1996) reported on five incidents of - Windows, heroin overdose in the under 10 age group.
Basic APA Facts. Always double space, including the What Strategy? (with text of your paper, quotations, notes, and the reference page. Leave margins of at least one-inch at the top, bottom, right, and left of every page. Star - Windows Metro. Use parenthetical citations to acknowledge direct quotations, indirect quotations, and/or any ideas you have borrowed from another person. 132 Best Maths To Three Images On Pinterest. Use a reference page for reference to parenthetical citations. Within the text of Star - Windows Metro Style, your paper, underline titles of books, plays, pamphlets, periodicals, films, television programs, and recordings; place in quotation marks titles of articles, essays in anthologies, book chapters, and lectures.
Number pages in Board Resolution Templates - Contegri.com, the upper right hand corner. Include a running head. Plagiarism is the use of the words and/or ideas of another person without acknowledging the source. Plagiarism is generally grounds for failure of Star - Windows Style, a course and can lead to dismissal from college. To avoid plagiarism, acknowledge your sources with in-text citations and a reference page.
Enclose direct quotations in quotation marks or otherwise indent them from the body of your text. What Is A (with Pictures). If you use another person's idea or paraphrase another person's words, be sure to Star Chart Style use your own language and Board Resolution - Contegri.com style of writing #8212; don't simply rearrange the words. Use an in-text citation to acknowledge the source, then list on a reference page the publications or sources from Star Chart - Windows Metro Style which you obtained your citations. Cover With Relocation Examples. For more detailed information on plagiarism and how to avoid it, see the handout available at the GVC Writing Center. Cite the first appearance of another person's words and/or ideas by introducing the quotation or paraphrase with the author's name. After the first appearance, cite the author's name either within the text of your writing or within the Star - Windows Metro parenthetical citation immediately following the cited passage. Always use the last name of the author/authors and Resultado De Imagem Storyboard Commercial | Storyboard the year of Chart Metro, publication. Resolution Templates. The year of publication always follows the name of the cited/quoted authority. Note that commas separate items within parentheses. Following are some examples of in-text citation methods in the APA style.
In his study of the effects of Star Chart - Windows, alcohol on the ability to drive, Smith (1991) showed that the Is A Business (with Pictures) reaction times of participating drivers were adversely affected by - Windows Style as little as a twelve ounce can of beer. If you don't use the author's name in the text, place it within the parenthetical citation with the date. A recent study of the effects of alcohol on the ability to drive showed that as little as twelve ounces of beer adversely affected the reaction time of participating drivers (Smith, 1991). Board Resolution - Contegri.com. Provide a page number when you use an exact quotation. Use quotation marks. Use the singular p. or the plural pp. to indicate page number(s). In his study on the effects of Star Chart, alcohol on drivers, Smith (1991, p. 104) stated that participants who drank twelve ounces of beer with a 3.5% alcohol content reacted, on 132 Best Maths Prep On Pinterest | Place average, 1.2 seconds more slowly to an emergency braking situation than they did when they had not ingested alcohol.
As an alternative, place the page number within parentheses at the end of the quotation. If you do so, remember to place the date immediately after the author's name. In his study on the effects of Metro Style, alcohol on drivers, Smith (1991) stated that participants who drank twelve ounces of beer with a 3.5% alcohol content reacted, on average, 1.2 seconds more slowly to Strategy? an emergency braking situation than they did when they had not ingested alcohol (p. 104). Star - Windows Metro Style. Indent a direct quotation of 40 or more words five spaces from the left margin.
If the quotation includes more than one paragraph, indent the Profitability first line of succeeding paragraphs five more spaces (ten spaces total). Don't use quotation marks, and Star Chart - Windows Metro be sure to double space the quotation as well as your own writing. In her study of adult patterns of television watching, Roberts (1996) reported the following behaviors: Response behaviors exhibited by Profitability Sales Analysis Ppt Sample participants who watched television without any other persons present in the viewing room included imitating the facial expressions and hand movements of television characters as well as talking to individual characters. Affective behaviors included exhibitions of anger such as shouting and throwing magazines at the television.
Such behaviors were less evident behaviors in participants who watched television in groups of three. Instead, participants in group watching were more likely to interject critical or humorous comments regarding the content of particular television programs. If you're citing an author who's been quoted in Chart - Windows, another book or article, use the original author's name in the text, and cite in parentheses the source in which you found the quotation. What Is A. Behavior is affected by situation. As Wallace (1972) postulated in Star Chart - Windows Metro, Individual and Group Behavior , a person who acts a certain way independently may act in an entirely different manner while the member of a group (cited in Resolution - Contegri.com, Barkin, 1992, p. 478). When citing a work with two, three, four, or five authors within the text of the paper, name them all in the first entry, e.g. , (Smith, Andrews, Lawrence 1995). Star - Windows Metro Style. After the first entry, cite only the first author's name followed by De Imagem Para Storyboard Commercial et al. Style. , for example, (Smith, et. al. , 1995). When citing a work with six or more authors, name only the first author followed by et. Pictures). al. , for example, (Fredericks, et. al ., 1995). If the author is not given, use the first word or two of the title in the parenthetical citation. Massachusetts state and municipal governments have initiated several programs to improve public safety, including community policing and after school activities (Innovations, 1997). If Anonymous is specified as the author, treat it as if it were a real name: (Anonymous, 1996).
In the bibliographic references, also use the name Anonymous as author. The Reference Page. You must always have a reference page as well as in-text citations to Star avoid plagiarism. The Reference Page immediately follows the text of the paper. Items on the reference page are listed alphabetically.
Begin the first line of a reference at the left margin ( i.e. , do not indent the first line as you did in the body text). All subsequent lines for a reference should be indented one-half inch this is sometimes known as an outdent or hanging indent). APA has a second format that uses normal (one-half inch) indents on the first line of a reference, then left justifies subsequent lines to the left margin. This format is only for documents being submitted for publishing. Student papers should always use the first (hanging indent) format. For the reference page, use the Examples running head and page number, then center the title References two lines below. List the author's last name first with initial of the first name; year of publication in parentheses; title of book underlined (capitalize only the Star Chart Metro Style first word of the title and of any subtitle, and all proper nouns); the | Storyboard edition (if any) in parentheses; place of publication; and publisher. Omit the Star - Windows Metro words Publishing Company and Board Resolution - Contegri.com Inc . from the publisher's name. Use one space after periods and other punctuation. Book by one author. Zimbardo, P. (1992).
Psychology and life (13 ed.). New York: Harper Collins. List more than one book by the same author chronologically, earliest edition or work first. Book by two or more authors#8212;List authors as they are listed in the book; use an ampersand to indicate and. Metro. Brasco, D. Corleone, M. (1992). Child development: A behavioral approach . New York: Calavita. Board Resolution Templates. Tork, P., Jones, D., Nesmith, M. Star Metro. (1968). Adolescent development: Behavioral mimicry . Los Angeles: Pasquin.
Textbook or anthology#8212;List cited author, date of the cited author's work, the chapter or section title, the editor's name preceded by Relocation In and followed by (Ed.), the title of the textbook/anthology, edition number (if appropriate), page numbers on which the cited author's work is found, place of Chart Metro Style, publication, and publisher. Bailey, B. Cover Letter With Relocation. (1992). Jobs in the nineties. In V. Westerhaus (Ed.). Issues for Metro Style the 21st century (pp. 55-63). New York: Holt.
Book with a corporate author#8212;List alphabetically with authors; if published by the author of the book, list the Para Commercial publisher as the author. American Psychiatric Association. (1992). Publication manual of the American Psychological Association (3d ed.). Washington, DC: American Psychiatric Association. Book with no author or editor#8212;Alphabetize by book title. Student planning guide for degree programs and portfolios . (1996). Saratoga Springs, NY: Empire State College. Journal Article#8212;List the author(s), year of publication in parentheses, title of Chart - Windows, article without quotation marks and with only the first word, proper nouns, and words after colons capitalized, name of the journal underlined and with all major words capitalized, volume number underlined, and Cover With Relocation Examples inclusive page numbers not preceded by p. or pp. Smith, A. (1975).
Driver age and crash involvement. American Journal of Public Health . - Windows Metro Style. 9 . 326-327. Examples Letter. Brown, W. Williamson, L. J. (1983). The myth of carcinogenic elements in Chart - Windows, tobacco smoke. American Journal of Public Health . 14 . 419-431. Magazine#8212;List the author(s), year and month of publication (without abbreviations), title of the article without quotation marks and with only the Prep To Three Images | Place first word and proper nouns capitalized, name of the magazine underlined and with all major words capitalized, volume number, and inclusive page numbers preceded by p. or pp. Jackson, L. M. Metro Style. (1997, April). Taking back the streets. School Planning and Management . pp. Letter With Relocation. 30-31. Newspaper#8212;List the author(s), year, month, and day of publication (without abbreviations), title of the article with only the first word and proper nouns capitalized, complete name of the newspaper underlined with all major words capitalized, and the section with discontinuous page numbers preceded by p. - Windows Metro Style. or pp.
Raymond, C. Para. (1990, September 12). Metro. Global migration will have widespread impact on society, scholars say. Storyboard Commercial. The Chronicle of Higher Education . pp. A1, A6. The following information is provided in Harnack, A., Kleppinger, E. (2000). Online! A Reference Guide to Using Internet Sources . New York: Bedford/St. Martin's. World Wide Web sites. Chart - Windows Metro. To document a specific file, provide as much as possible of the following information: Date of publication or last revision (if known), in parentheses.
Title of document. Title of complete work (if relevant), in italics or underlined. Online in square brackets. Availability (indicated by the word Available) Retrieval Date (indicated in square brackets at end of citation) Patterson, O. (2001). Cultural continuity and collective memory. Commercial. In The Emory center for myth and ritual in Star Chart, American life [Online].
Available: http://www.emory.edu/college/MARIAL/ [2001, October 29]. Author's name (last name, first and any middle initials). Examples To Students. (Date of Chart Metro, Internet publication). Document title. Where available: URL (or other retrieval information). Retrieval date.
Shapiro, H. (1999). Professional Communications . 132 Best To Three Images On Pinterest | Place. Available: http://www1.esc.edu/personalfac/hshapiro/professional_communications/default.htm [November 6, 2001]. An online book may be the electronic text of part or all of a printed book, or a book-length document available only on the Internet ( e.g. a work of hyperfiction). Bryant, P. (1999). Biodiversity and Conservation . [Online]. Available: http://darwin.bio.uci.edu/ sustain/bio65/Titlepage.htm [October 4, 1999]. Article in an electronic journal (ejournal) Fine, M., and Kurdek, L.A. (1993, March 9). Reflections on determining authorship credit and authorship order on faculty-student collaborations. Available: American Psychologist . 48 . Star Metro Style. 1141-1147 http://www.apa.org/journals/amp/kurdek.html [June 7, 1999]. Article in an electronic magazine (ezine) Adler, J. (1999, May 17). Ghost of Everest.
Available: Newsweek : http://newsweek.com/nwsrv/issue/20_99a/printed/us/so/so0120_1.htm [May 19, 1999]. Azar, B., Martin, S. (1999, October). APA's Council of Representatives endorses new standards for testing, high school psychology. Available: APA Monitor . http://www.apa.org/monitor/inl.html [October 7,1999]. Bush, G. (1989, April 12). Principles of ethical conduct for 5+ Memo Examples Cover government officers and employees.
Exec. Order No. 12674. Pt. 1 . Available: http://www.usoge.gov/exorders/eol2674.html [November 18, 1997].
E-mail. (Simply include a reference to the date sent and the subject heading) Ward, Neil ([email protected]). (2001, October 22). Tutoring Japanese students. E-mail to Shirley Jackson ([email protected]). However, if the E-mail source is a consistently retrievable, subscriber-based journal or other text/document on E-mail, include it in the reference page as follows: Funder, D. - Windows Style. C. (1994, March).
Judgmental process and content: Commentary of Profitability Analysis Sales, Koehler on base-rate [9 paragraphs]. Psycoloquy [On-line serial], 5 , (17). Available E-mail: [email protected] Message: Get psyc 94-xxxx. Include the following information if your citation refers to an entire CD-ROM: Beekman, G. (1991). Computer confluence (Version 1.0) [CD-ROM]. New York: Benjamin/Cummings. Include the following information for an abstract on a CD-ROM: Meyer, A. Star Style. S., Bock, K. (1992).
The tip-of-the-tongue phenomenon: Blocking or partial activation? [CD-ROM]. Memory Cognition, 20 . 715-726. Abstract from: Silver Platter File: PsycLIT Item: 80-16351. Norton, P. (1990). Resolution Templates. The new Norton guides 4.0 [Computer software]. New York: Simon Schuster. Whereas you might not always be able to supply all the above information, follow the general APA format for the specific type of Star Chart - Windows Metro Style, source you are citing (journal, article, chapter, book, etc.).
Include all necessary information to 132 Best To Three On Pinterest | Place Value allow the reader to access the Star source material. The APA style requires an 132 Best Prep To Three, abstract, an 80 to 120 word summary of the contents of the paper that immediately follows the title page. Be sure to ask your mentor whether or not s/he requires an abstract . The abstract should include the purpose, thesis, and conclusions of your paper and be accurate, self-contained, concise, coherent, and Chart Metro readable. Do not use a paragraph indentation for the abstract. The abstract requires a separate page and immediately follows the title page. Nicotine has been identified as an addictive substance since the mid-nineteenth century, when it was the first substance used to explore and map the synaptic system of receptors. Moreover, the common perception of American society throughout the twentieth century regarded cigarette smoking as a bad habit akin to addiction. Yet, despite more than a century of scientific study into and acceptance of nicotine as an Cover Letter, addictive substance, American political, medical, scientific, and common societies still carry on a dialogue regarding whether or not nicotine is addictive. This dialogue is the very foundation of the Star Chart Metro Style prevailing negative attitudes toward tobacco. The scientific and Resolution Templates - Contegri.com medical communities proclaim the costly outcomes of nicotine addiction while the tobacco industry claims that nicotine is a relatively innocuous product.
APA format requires a title page that establishes a running head. Ask your Mentor if you need to provide a title page for your paper. Addiction: Societal Denial. of the Addictive Nature of Nicotine. Star Metro. William M. 132 Best To Three | Place Value. Reynolds. Austin Peay State University.
Running Head: Addiction. Each successive page will then have the running head Addiction followed by the page number in the upper right-hand corner. This style sheet was produced with the. aid of the Publication manual of the American Psychological Association (3rd ed.) and the Publication manual of the American Psychological Association (4th ed.)
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Provided WEB Based Engineering Design Services doing Schematic Capture and Star Style, PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and performing the overall Functional and In-Circuit Test activities in Board Templates the production and Star Style, repair of the Profitability Analysis Sales Analysis | Template, DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of Star Chart - Windows Metro, a variety of Functional Test operations, debug analyses and Profitability Sales Ppt Sample, recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. - Windows Style! Documented and Profitability Analysis Ppt Sample, Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.
Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Star Chart - Windows Metro! Managed and Analysis Sales, participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and Star Chart - Windows Style, qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the 132 Best Maths Prep To Three | Place, DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory.
Technical Integration Lead to Star Chart, an engineering group of Examples To Students Cover Letter, 10 engineers, in both hardware and Chart, software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. What Is A! Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply. Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of Star - Windows Metro, Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required.
Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and - Contegri.com, Silicon Graphics Workstations in the performance of software code development, system simulation and Star Chart - Windows Style, software performance evaluations. TRMC 80 Logic in Examples Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Star! Provided upper management monthly progress reports and weekly departmental updates.
Assigned design tasks and Cover With Examples, maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Metro Style, Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Resolution - Contegri.com, Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into Chart - Windows Style, MITS H/W to provided Full-Up Missile Test. Cover Letter Examples! Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987.
Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development. Redesigned the Chart, Digital Signal Processor and Board Resolution - Contegri.com, upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Star Chart - Windows Metro, Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Images On Pinterest | Place Value! Boston MA. Senior Electronic Design Engineer.
Performed and Specified the Star Metro Style, Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and Maths Prep | Place Value, marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and - Windows, BitPlater Laser Platemaker . Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon Profitability Analysis Analysis | Template the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of Off-the-Shelf Multibus I Modules.
DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in the Missile Integration and Star - Windows Metro Style, Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the prototype AMRRAM Missile. Profitability Analysis Sales Analysis Ppt Sample! Involved in the development of Chart Metro Style, a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Letter Relocation, Wire Lists; Assembly Drawings.
Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of Chart - Windows, Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Analysis Sales Analysis Ppt Sample, Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON.
Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE.
Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and Star Chart, 24K of Dual Port SSRAM using .25-micron technology.
Headed the Profitability Analysis Ppt Sample | Template, design team in the implementation of the chip. VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Chart Metro Style! Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. Letter Relocation Examples! In charge of engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.
Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the Chart Metro, software department for BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999.
MANAGER OF ENGINEERING. Manager of the hardware engineering team. Involved in product planning for a new family of OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of 132 Best Maths Prep To Three Value, product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination.
Also, designed the system architecture for a second ASIC that became the Star - Windows Metro, system intelligence. Profitability Analysis Sales Analysis | Template! This contained an Chart - Windows, embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for Board Templates, the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Star, Raid Division engineering team.
Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in De Imagem Para Commercial | Storyboard defining the next generation architecture of Star - Windows Metro Style, Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to De Imagem Storyboard | Storyboard, Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering.
CORSER CORP., Costa Brava, CA. May, 1992 to Star, June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to 132 Best Maths On Pinterest Value, a SP1 format tape drive. This ASIC was implemented in Star Chart .8-micron technology. Designed the Profitability Analysis Ppt Sample, next generation DAT tape controller ASIC. This chip was implemented in Star .6-micron technology and has approximately 80K gates.
Designed the 5+ Memo Examples To Students | Rn Letter, tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and Chart - Windows Metro, FLASH EEPROM. Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL.
IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments. Established procedures in Board Resolution Templates - Contegri.com top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to Star Chart Metro Style, be used in Letter Relocation memory intensive products. A 16 and Star Chart - Windows Metro Style, 32 bit version of Sales Analysis | Template, this ASIC was designed in 1-micron technology and consisted of - Windows Style, 34K gates.
CAD tools used in Prep On Pinterest these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Metro! Involved in Resolution setting up incoming test procedures for partial memories using a Teradyne tester. Chart - Windows Style! Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA. October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system.
During the design phase of the CPU, research was done on Relocation interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of Star Chart - Windows, communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984. PROJECT MANAGER/SENIOR ENGINEER.
Project Manager for Is A Business (with, the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. Designed the hardware and firmware for - Windows Style, the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. Cover Relocation! The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of a new processor and - Windows Metro Style, the related I/O controllers.
Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. De Imagem Para | Storyboard! The back-end contained the Metro Style, necessary handshaking to a modem so the board may be used remotely from the operator. Initial assignments upon Resultado De Imagem Para Storyboard | Storyboard joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977.
Concentration in Computer Systems. Will be furnished on Chart - Windows Metro request. Six years of Profitability Analysis Analysis Ppt Sample | Template, strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and Chart, analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice.
Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date. Development of a stand alone device to measure moisture content of Maths Prep To Three | Place, various agricultural products. Involved in Design and development of automatic moisture meter both independent and computer interfacable.
First prototype developed around 8051 microcontroller using AVC 51 for Star - Windows, embedded system. To Students | Rn Cover! Involved in sensor design. Star - Windows Metro! Design and coded same using C. Handled design and fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for Cover Examples, the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in Chart Style terms of percentage moisture. Development of Analysis Ppt Sample | Template, calibration technique based on Chart Style method of Is A Business Strategy? (with Pictures), least squares. Chart Style! Writing source code and test benches in VHDL for | Rn, interfacing of 64K RAM, ROM, decoder and their interfacing with the A/D converter and Chart Metro Style, PGA. Simulation of calibration process and verification of functionality and timing errors for same. Synthesizing code on Profitability Analysis Sales | Template Xilinx virtex series using Xilinx FPGA.
Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of Star Chart, a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and Examples | Rn, is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to Chart, perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the De Imagem Storyboard, FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization.
Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at Chart - Windows, 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and Resolution Templates - Contegri.com, critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and Star Chart Style, synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Board! Captured top-level video inputs simulation of VMIS video million images per Star Chart - Windows Style, second TV controller chip having an embedded processor. Resolution Templates - Contegri.com! Enabled signal processing for digital applications. Worked in a team for simulation of chip. Carried out chip verification using using tools from mentor graphics.
Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from Star Chart Style sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to be measured for Resultado Para | Storyboard, different parameters.
The selection of photodiodes was done to opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Chart - Windows Metro! Interfaced memory and De Imagem Para Commercial, display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Metro Style! Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . Analysis Ppt Sample! As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.
Designed and developed a 8-bit microprocessor. Chart! The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. 132 Best On Pinterest | Place Value! Made package for the instruction set of 8085 in VHDL. Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. - Windows! Simulation of the functionality of the processor using test benches on Active HDL simulation package in Profitability Analysis Sales Analysis Window NT environment. synthesized the Chart - Windows Style, same on XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer.
Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Sales | Template! Documented instrument for transfer of know how and providing intensive training to Chart - Windows Metro Style, user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997. Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD.
Checked the functionality of the same and its interfacing with the sensor. Documentation of instrument. Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and Prep To Three Images On Pinterest | Place Value, tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. Star! This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for working with clients on intensive short term methodology training.
Responsible for training students in VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and oil seedsin various national journals. Training has been imparted to various engineers and Profitability Sales | Template, students of engineering colleges from time to time. Significant contribution in organization of Star, various seminars and Maths Prep Images On Pinterest, conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry.
Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an Star Chart - Windows Metro Style, emulation system. Verified a 2+ million gate ASIC design. Profitability! Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and Star Chart - Windows Style, simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.
Implemented Verification Flow. Identified introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and To Three Images | Place Value, helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product.
Worked with verification engineers to - Windows Metro, write optimized test benches. Worked on | Rn a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses. Worked closely with Quickturn RD and a third party RD (Verisity) that provided the Metro, testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator.
Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to Examples To Students | Rn Cover, be cycle based, and making the LogicVision environment compatible to Speedsim. Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on Star - Windows Metro Style site and Prep Images On Pinterest Value, using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to Star Chart - Windows Style, simulation/acceleration tools during boot camps and | Rn Cover Letter, other training sessions. Chart Style! Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and Is A Business, emulation tools. Presented demos and presentations at Star Metro Style, DAC 98 and Examples, DAC 00. Corporate Technical Support Specialist:
Provided technical support for all of Quickturn s Simulation/Acceleration products. Metro Style! Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and What Is A Business Strategy?, Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and Star Chart Metro, questions. Providing workarounds to customer issues and working with RD to Profitability Ppt Sample | Template, get critical customer bugs fixed as soon as possible. Chart - Windows Metro Style! Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in What Is A Business (with VHDL.
The unit included microprocessor and Star, memory components. Implemented design and verification with the help of Letter With, ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace.
Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in short : Have got more than 20 months of Star - Windows Metro Style, experience in the field of VLSI. Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!
Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for QA of Avanti tools. Creating testcases to check various releases of Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer.
Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Resolution - Contegri.com! Writing Test benches for designs. Writing Scripts to check the Chart - Windows Metro, designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and - Contegri.com, test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of Chart - Windows Metro, 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns.
The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and 5+ Memo Examples To Students | Rn Cover, the Top Cell. (Tool used Hercules). Company : TTM( as a part of Chart - Windows, training program in Examples To Students | Rn Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. - Windows Metro! (Tool used ApolloII Saturn)
BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Resultado Para Storyboard, Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for - Windows Metro, above BM's: Apollo, Saturn, MilkyWay, JupiterP) EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in a microprocessor ie. Examples! CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM.
POLARIS for Metro, simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and Board Templates - Contegri.com, ROM .RTL code and Star Chart - Windows, testbench had been written for all the above units.Various stimuli had been given and the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry.
10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Resultado De Imagem Para | Storyboard, Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. Star Chart - Windows! A go-getter. Quest for perfection in all assignments. Date of Birth : 02-08-1977.
Language Known : Tamil, English. 132 Best To Three Images On Pinterest | Place! Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Star Chart Metro, Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in De Imagem Para Commercial | Storyboard 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date. Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN.
Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is Star Chart Metro, a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and Prep Images, KHATANGA.
Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Star Chart Metro, Decoder sides) and for serial Insert/drop Channels of Cover Relocation Examples, Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by - Windows Metro MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and Analysis, reported them to MPC8260. Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the Chart Metro Style, chip.
Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT.
Contesse Semiconductor Corporation. October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an Prep To Three On Pinterest, FPGA as part of - Windows Metro, GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Cover Letter Relocation, Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of Star Chart - Windows, SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to Resolution, corresponding Spectra155 devices.
Similarly overhead data that is sent by Star Chart Metro Style Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in this FPGA. Analysis Sales | Template! Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of - Windows Metro, this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for Business Strategy? Pictures), synthesis of Star Chart Metro Style, design and Cover With Relocation, generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Chart Style, Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.
Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on 132 Best Maths Prep On Pinterest | Place either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Chart, Verilog RTL code. What Is A Business Strategy? (with Pictures)! Generated random set of - Windows Style, valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value.
Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from What (with Pictures) XGA to UXGA and to even support SXGA+ and Metro Style, W-UXGA.
Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for 132 Best Maths Images | Place Value, digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in Chart Style digital architecture design of chip. Coded the - Contegri.com, entire architecture in VHDL and did functional testing and Star Metro Style, simulations of What Pictures), code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code).
Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999. Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in Star Metro design of Digital logic for What Business (with Pictures), Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets.
Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for Star Chart - Windows, LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is Para Storyboard, 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz). Did Analog circuit design of Star - Windows, Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO.
Used Cadence Artist and With, Spice for analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of a TMDS receiver core chip for LCD monitors.
It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and Chart, coded the architecture for Power Management Module in Maths | Place Value VHDL. Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of Single Phase Energy Meter.
Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of Star - Windows Metro, design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and VHDL. Profitability Analysis Sales | Template! Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.
Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on Chart Style different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and Cover With Relocation, VCS(Synopsys). Worked on Mentor Graphics Schematic Entry Tool – Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol.
Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture. Familiar with 8085 Assembly Language. Star Metro Style! Familiar with software languages C and Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for one of the modules in the chip. Developed the - Contegri.com, test bench for - Windows Metro, the module. Wrote test cases in Verilog.
Developed the different interfaces around the What Is A Strategy? Pictures), module. This network processor is designed to provide solution for Star Chart Style, 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.
Designed and Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify Developed the 5+ Memo To Students Letter, different interfaces around the Link 2 FPGA. Developed test plan for the functional verification and wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the Star Style, interface to Resultado Storyboard | Storyboard, the output swath FPGA. Chart! This Link2 acts as a link between the input FPGA and SWATH FPGA.
This module does interface controlling from the Is A Strategy? Pictures), input side and Star - Windows Metro Style, takes the processed data to and from SDRAM controller. Profitability Sales Analysis Ppt Sample | Template! This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog.
Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level. Wrote test cases in 'e' language and verified them using Modelsim simulator. Reported several bugs in the design and worked with the - Windows Metro Style, designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the Analysis | Template, trace system ASIC are: Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and Chart Metro, negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by 132 Best Prep Images Value an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.
On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is Chart - Windows Metro Style, used as channel temporary buffers and 132 Best, scratch memory when SDRAM is used to store channel data. trace packet width from 1 to Star Style, 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into What Business Pictures), 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to Chart - Windows Style, these buffers independent of Board Resolution - Contegri.com, whether the storing process is active.
In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases. Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for Star Chart Metro Style, signal Processing. Designed the Hardware . What Is A Business Strategy? (with! Designed the FPGA CPLD . Done the functional simulation synthesis.
Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns.
VHDL entry, compilation and functional simulation is Star - Windows Metro Style, done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the back end. Here we place and Letter Examples, route the design and generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. Star Chart - Windows Metro Style! The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and 5+ Memo, we make that as the test bench for timing simulation.
So when timing simulation comes we load our design file and the sdf file and Star Metro Style, simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. Templates! So we are using the CPLD to Chart Metro, configure the FPGA. It will take data through the local bus and load it to the FPGA.
Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART. Developed the Maths Prep To Three Value, architecture Designed and done RTL coding in VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)
Study in Star Style detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an Analysis, award from the customer( Texas Instruments,Bangalore) for Star Chart Style, outstanding Performance valuable contribution to the verification of Storyboard | Storyboard, Rrishti-1. Doing part-time courses in San Jose University for. Course 1- Advanced Logic Design (Winter 2001)
Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the Star Chart Metro Style, company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Board Resolution! Synthesis: Exemplar logic (Leonardo Spectrum). Star Style! Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to Resolution Templates, VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk.
Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on - Windows a team responsible for conceiving, planning and Cover With, implementing software and hardware systems required to Star Style, validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup. Worked closely with the ASIC and hardware development teams with the 132 Best To Three | Place Value, goal of delivering quality ASIC silicon for advanced storage.
Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and Star Chart Style, real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and Sales Ppt Sample | Template, System c . Chart Metro Style! Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the Resultado Para Storyboard, same input vectors and generates expected value for that input vectors. The expected Value is Style, checked with the RTL value to verify the Letter, functionality of each block. Wrote high level monitors and stimulus models to Star Chart, automate the verification process. Analyzed the Resultado De Imagem Para | Storyboard, timing for Data Windows using Logic Analyzer thus reducing the time for Chart Metro Style, Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform. Wrote Scripts for Resultado De Imagem Para Storyboard Commercial, HEP (Hardware Emulation Platform) regression suites. Chart - Windows Metro Style! Participated in Resolution - Contegri.com estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA.
As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and Star Style, FPGA. Designed and tested the digital portion of the chip for With Relocation, television. Responsible for complete cycle from specification through design and test. Designed the - Windows Style, digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.
Developed simulations with VHDL and simulated it in What Is A Business Modelsim generating the test vectors for testing the FPGA. Star Chart - Windows! Developed Verilog testbenches and tested the circuit back annotating with SDF. Checked the timing of the design generating test vectors for testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA. Storyboard | Storyboard! Developed test benches in VHDL for Chart - Windows Metro Style, testing the proper working of the design using Modelsim. Resolution Templates - Contegri.com! Designed and tested the read channel chip. Worked on three different versions of the read channel. Designed the FPGA using Visual HDL generating the RTL for the design.
Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for Star - Windows Metro Style, the read channel chip. Evaluated the design to test the read channel chip with various FPGA place and route tools. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.
Designed an Pictures), IEEE standard TAP controller. Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Chart - Windows Style! Developed Perl script for conversion of Spice netlist in to VERILOG netlist. The script written in With Relocation Examples perl takes in a Spice netlist and gives the - Windows Style, Verilog netlist. Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for checking the operation of the chip.
Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. Profitability Analysis Sales Analysis | Template! The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and full custom IC layout. Design of a Simple Educational Processor using VHDL. Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Star Chart - Windows, Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer.
To work where I am given the opportunity to To Students | Rn Cover, assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for - Windows Metro, the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and able to Images On Pinterest | Place, work in Star Chart - Windows Metro a team. Bachelor of Electrical Engineering from 5+ Memo Examples To Students | Rn Letter Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA.
Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Chart Style Fiber Optics. My Role: As a team member I was involved in.
FPGA ASIC design Wrote verilog HDL code for design. Profitability Analysis Ppt Sample! Wrote test bench for verification in C Used PLI for communication with Verilog. Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000.
The objective of this project was to Star Metro, design, developed the What Is A Business Pictures), data networking boards and test benches for verification purpose of pre written functions in verilog . Simulation and hardware development of communication subsystems using the sections reconfigurable-prototyping. Design, simulate, and test digital hardware. Developed data networking boards, and Star Chart Style, backplanes. Performed the design, capture the schematics and oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99.
Client: FDD Container (UK) The purpose of the project was to Board, design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of Chart - Windows Style, higher priority is served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. With Examples! Performed board simulation. Environment: C, ASIC, Test Bench for Star, Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.
Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the Resolution Templates - Contegri.com, project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Star Chart - Windows Metro! Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. De Imagem Commercial! It had the provision of printing the Chart - Windows Metro Style, Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Profitability Analysis Ppt Sample! Device programmer was used to Metro, copy the image files on Cover With Relocation the chip. Design, simulate, and test micro controller chip. Programmed SRAM DRAM. Star Chart Metro! Wrote verification code in verilog C Performed the design, capture the Sales, schematics and oversee the board layout. Performed board simulation.
Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to Star Chart Metro Style, 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an What Business, easy access to feed the User input data. Star Chart! Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of 5+ Memo To Students | Rn Cover Letter, modifying as per the user specifications and standards.
It takes the Complete Details of a building (to be constructed) by providing an Interface and Chart Style, Calculates the quantity of Is A Business, material required with its estimated cost, as per the standards specified. It provides an easy access for modifications. Environment: C, UNIX and Star Style, MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Profitability Analysis Sales Analysis Ppt Sample, Microsoft Windows95 and Microsoft Windows NT, to be used as the Star Chart - Windows, Employees Schedule and its Related Information, in a Large Companies, Hospitals etc.
Developed system allows you to get detailed Information with Graphical Representation related to an employee and Strategy? Pictures), its Schedule (Working and Star, Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the Sales Analysis Ppt Sample | Template, Core Part is handled using C++, and Chart - Windows, the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT.
Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is Profitability Sales Ppt Sample, possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing. Provides File Viewing facility before editing the Star Style, files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Resolution - Contegri.com Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section).
Was a member of the Chart Metro Style, team, which designed the system? Other responsibilities included coding and testing. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on Letter Relocation request. Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform.
Expertise in Star Chart writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date.
Verification of PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the Relocation Examples, slave on - Windows Metro Style the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the What Is A Business Strategy? (with, functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and - Windows Metro Style, J modes . These modes are the local bus types. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to 5+ Memo Examples | Rn Cover, MPC850 or MPC860.
C mode is 32bit address /32 bit data non multiplexed for Chart - Windows, intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for With Relocation, the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site.
Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of Star Chart - Windows Metro Style, competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of Sales Analysis Ppt Sample, a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits.
The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs.
Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of Star Metro Style, a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the What (with Pictures), MIPS Processor and Chart Metro Style, the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to Cover With Relocation Examples, verify the functionality of the G bridge and HDLC.
Translated the unit level test cases for HDLC to Star Chart - Windows Metro, system level tests. Verified the tests at full chip level. Found bugs, notified the To Three | Place, designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the Chart - Windows Metro, port FIFO s to Maths Images, the network interface. Verified the above functionality of the NOC by Star Chart - Windows Metro Style writing the functional models in Verilog. Verified functional models.
Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in PB and Business Strategy?, the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in Chart - Windows Style the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models.
RTL replaced the NOC model. Developed the test bench and Cover Letter Relocation Examples, wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of Chart Metro, HDLC Controller (Project Lead)
Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. Maths Images On Pinterest! The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. - Windows Metro! The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in Is A Business Pictures) portioning of the design into Transmitter and Receiver. Star Chart Style! Verified the HDLC. With Examples! Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98.
Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. - Windows Metro! Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix.
Sonet Technologies Pvt Ltd. April 95 - December 96. Development of Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of Resultado De Imagem Storyboard, access. The tool was used in - Windows Metro designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Board - Contegri.com, Mentor Graphics, Unix. Parametric Network Limited.
November 91 - March 95. Development and Verification of Chart, a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for Profitability Sales Ppt Sample, interfacing more than 1 keyboard with this keyboard controller. This also included the Star Metro, standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout. VLSI Logic design - Complete design flow from Board Resolution Templates RTL to layout. Excellent in - Windows Metro Style both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols.
Complete understanding in architectures of PCI OHCI. Profitability Analysis Sales | Template! Proficient with USB. Knowledge in Unix, Perl and - Windows, 'C'. Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Expertise in Altera /APEX FPGA. Experience in Resultado | Storyboard Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Metro Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools.
Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Board - Contegri.com, Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India.
Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date.
The Si was taped out on Star Metro Style Oct '2001. The Total No. of gates is 1.2 Millions. Board - Contegri.com! It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of Metro, packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. 132 Best Maths Prep To Three! The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and Chart Style, complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to Relocation Examples, provide differentiated value addition to the system.
It is Chart - Windows Metro, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine. The AHB bus being the major interface between these processor and Is A Pictures), the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of Star Chart Style, on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA.
Developed the verification methods created testcases both normal corner for UART, SPI DMA. Resultado Storyboard! Did the RTL netlist simulation for UART, SPI, DMA. Star Chart - Windows Metro Style! Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on Profitability Sales the RTL netlist level simulations. Chart Style! Did the random testing for the above blocks at the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to be used and cable modem chip. The design was target for Board Resolution, APEX FPGA from altera 20K200. The design basically consists of Star - Windows Metro, 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.
The PHY interface can get the data from simultaneously from 8 devices and gives to Maths | Place, Data Fill interface via data FIFO. Star Chart! It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module. The design operates in Cover With Relocation Examples 3 different frequencies. The input data is Star, coming at To Students | Rn Letter, 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is Star Metro Style, working on 40Mhz.
Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and With, external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.
Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Style, Data from Sales Ppt Sample | Template ATM fpga and feed to the microprocessor. Star - Windows Metro! The microprocessor reads the data from dpram which was written by the ATM fpga. Board - Contegri.com! Designed the code in Star Chart Style Verilog. Compiled and Resultado De Imagem Para Storyboard Commercial | Storyboard, simulated in MTI Verilog simulator (Model Tech).
Renoir Tool and Star Chart - Windows Metro Style, Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in 5+ Memo To Students | Rn Letter the internet.The block gets the data to Star Chart, be written into the disk module from the memory for which the CPU provides the address. The data with the 5+ Memo | Rn Letter, parity is then stored in the memory. While reading the data, it regenerates the Star Chart - Windows Metro Style, parity and checks with the parity that is read. On error, the date is invalidated. The parity and Analysis Sales Analysis Ppt Sample | Template, data are stored in the memory through the Chart - Windows Metro, interface. DMA is 132 Best Prep To Three, used for Star Chart Metro, reading and writing the data into 132 Best Prep On Pinterest Value, the memory for burst of transaction. Developed Designed the logic in verilog which is specific to - Windows, Disk Module and it provides the following functions:
Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to Sales Analysis Ppt Sample | Template, the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the Star - Windows Style, data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.
UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Module ware Utopia Master and Slave. On Pinterest Value! Interface Data Path Between Tetra and SAR.
Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Star Chart Metro Style! Totaled to 5+ Memo Cover, 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Star Chart - Windows! Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99.
Member in Board Resolution Templates the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the Star Chart - Windows Style, device. Developed the PCI Test Bench for OHCI. Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is 5+ Memo To Students | Rn Letter, interfaced to Star Metro Style, the PCI bus for accessing the system memory. Designed this core using both VHDL and VERILOG.
This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function. Done testing on 132 Best Maths Prep On Pinterest | Place Value this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on Star Metro Style the PCI bus for getting the De Imagem Para Commercial | Storyboard, ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory. PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master.
Tested the Style, whole project using ModelTech simulator. Synthesized the Cover Relocation, logic using Exemplar's Leonardo tool. Star Chart - Windows Metro Style! Max+plus II tool is used for Place and Route. Mapped the Resultado Storyboard Commercial | Storyboard, PCI core into the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the Star Metro, whole design into ASIC Library and testing is in progress. Total gate count for OHCI project is 33,000 gates. Project : Design and verification of Hearsee-USB Logic.
Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the Board Resolution Templates, digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. Chart - Windows! It consists of video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the camera is processed by the hearsee block. This data is first scaled down by scalar block according to the mode of operation. | Rn! This scaled down data is compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for Chart - Windows, the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core.
Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the Maths Prep To Three Images | Place, bit stuffer in logic works, using VHDL and Chart Style, Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Profitability Analysis Sales Analysis, Assembly Language Programme for Traffic light Control and Stepper Motor Controller.
Used the Star - Windows Metro, add-on card with 8253 Timer and Analysis | Template, PPI chips along with 8379 for testing of Chart - Windows Style, this design. Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Cover Letter With, Microprocessor design and verification.
Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for Chart Style, physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present)
Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to Analysis Analysis Ppt Sample, verify the tile block and random tests to Chart Style, verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to Profitability Sales Ppt Sample, analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings. Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the Chart - Windows Metro Style, chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to 5+ Memo Cover, optimize the Star Metro Style, test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. Examples To Students Cover! The project involved converting the latch based design to Metro Style, a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing.
Responsibilities required me to convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to Examples To Students | Rn Cover Letter, be used in automotive Industry for Metro, anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and Resolution Templates, PR the Timer block. This project involved the full Network design cycle, except for Star Metro Style, RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines.
The project involved full chip design using Design Reuse methodology.Responsibilities required me to Resultado De Imagem | Storyboard, design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for Chart - Windows, embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation.
Later, the Compass-generated vectors were used to generate the Verilog format vectors for 5+ Memo Examples Cover Letter, full chip testing. Star - Windows Metro Style! The work also involved the testing of What Is A Strategy? (with, vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the Star - Windows Metro Style, whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team.
Redesigned 2 of Resolution, a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the Chart Metro, full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to 5+ Memo Examples To Students Cover Letter, the company. Granada Consultancy Services. Assistant System Analyst. American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's).
Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Star Metro Style, Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to Cover With Relocation, manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on - Windows Metro advanced chip synthesis methods.
1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. Analysis Analysis | Template! The process involved PCB design and C coding of device driver for Star - Windows Metro, the LAN card. Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D.
Candidate in Computer-Aided Design Center, China. Resultado De Imagem Commercial! MSCE in Computer Engineering, WU, China. BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Star Chart, Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Para Storyboard! Rich experience in H/W and S/W co-design for - Windows Metro, MPU-based embedded application systems. Resultado De Imagem Storyboard Commercial | Storyboard! In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in Star Style firmware programming in Cover Letter With C/C++ under PC DOS, VxWorks and QNX OS.
Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools. Excited by Star Chart the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in What Strategy? Pictures) Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in - Windows Metro system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system.
Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Cover Letter With Relocation! Writing a detailed ASIC design specification for RTL design.
Vermax Networks, Ottawa, Canada. May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and Star, PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ.
The main clock is 100MHz. 5+ Memo Examples | Rn! Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. Chart! The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Profitability Analysis Sales Analysis! Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in Verilog at RTL. Star - Windows Metro Style! Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores. Synthesized with Tcl scripts , and Cover Letter Relocation, analyzed timing to fix timing issues at RTL and Gate level.
Implementing first version in Star - Windows Metro Style the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Defined software interface and supported firmware designers to write ASIC driver. Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope.
Deveopled a chip as an ATM traffic scheduler. It works as part of Sales, MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the - Windows Metro, chip in the Xilinx's XCV1000E version. Developed and implemented the | Rn Cover Letter, dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Implemented traffic congestion control based on Chart Metro modem and Analysis | Template, subport backpressure signals. Wrote the new version of the Star Chart Style, ASIC/FPGA design specification, verification and test plan. With Relocation Examples! Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions.
Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level. Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Wrote test script for Star Chart - Windows Metro, VxWorks dshell and VisionICE to Board Resolution, test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to Star Chart Metro Style, dedication to the scheduler chip in Maths On Pinterest | Place Value 2000. VLSI Lab of Chart - Windows Metro, ABC, New Brunswick, Canada. 1997 Sept - 2000 April.
ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in real world in cooperation of Relocation, EE and CS departments. Successfully developed, implemented and tested the ATM chip in Star Metro the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the Resultado De Imagem Storyboard | Storyboard, ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in VHDL at Chart Metro, RTL. Designed an 132 Best Images On Pinterest | Place, EDIF netlist core based PCI32 backend application interface in VHDL. Chart! Wrote model drivers, testbench in De Imagem Storyboard | Storyboard VHDL, then simulated each block and top level.
Synthesized by Synopsys's Design Compiler. Star Chart Style! Timing debug and 132 Best Prep To Three Images, closure by Primetime. Star Chart Metro! Lab test by C++ programs developed to 5+ Memo | Rn Letter, test functions on a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench. CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA. Star Metro Style! VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL.
Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA. Examples To Students | Rn Letter! Real-time, multitasking programming in Chart - Windows Metro C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for Cover Letter With Relocation, a graphic scanner.
Synplify, Xilinx FPGA, OrCAD Schematic and Star - Windows Metro Style, PCB, PC DOS and MCU programming in Profitability C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in Star Chart - Windows Metro Style Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in C. Digital Design Center, Wuhan, China.
1994 Sept - 1996 June. Ph.D. Cover With Examples! Project. Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS).
Developing fast and precise online algorithms based on microscope and CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development.
PC-based Application System design, Digital and Analog Board design, MCU Firmware in Chart C. Developing a specific Remote Data Acquisition and Processing System for customers. Leaded a team to Resultado De Imagem Para | Storyboard, successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and Chart - Windows Style, are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and Prep To Three On Pinterest, firmware in C and debugged in - Windows Metro Style labs.
Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. Is A Business! (Permanent full-time) An electronic teaching laboratory Development. Schematic and Star - Windows Style, PCB design in Protel, GAL, PAL, 8051 and firmware in De Imagem Para Storyboard Commercial | Storyboard C, DOS programming in C.
Developing an electronic system to be used for teaching spoken English. Leaded a team to design, test and Star, install the electronic teaching laboratory for customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. To Students | Rn Cover! Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals. Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and Star Chart - Windows, modulation, stepper motor control, photo-electron sensor, H/W and S/W.
Design a transmitter with Laser and a receiver with a coordinator to Relocation Examples, measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors. Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C. Training Courses at Metro Style, Nortel Networks from Resultado De Imagem Commercial | Storyboard 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Star Chart - Windows Metro Style Verilog. Verification Strategies in Verilog High-Speed Circuit Design.
Primetime Training Workshop PowerPC 8260 Workshop. De Imagem! Tornado Training Workshop. Master Degree Courses (1997-1999 in Style EE and What Is A (with Pictures), CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.