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Sorry for Sugarflair_colour-Chart.jpg (700?891) Palettes the inconvenience but it#8217;s part of the complete revamp of Relations, my web site. I#8217;ve made things much simpler. Sugarflair_colour-Chart.jpg Palettes | Pinterest! The fiction page lists all my novels in series order. The freebies page has all my free books, short stories and Essay Outline. Testing Animal audio shorts. Nothing but good time ahead!! 105 Years Ago, Jack Died.
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And, honestly, get away. Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest! So when I saw this headline in the NY Times “ Which Force is More Harmful to the Arts: Elitist and Populism ?” I did what I often do. I looked up what words really mean. Populism: support for the concerns of ordinary people. Elitism: the advocacy or existence of an elite as a dominating element in Essay Outline. Argumentative Testing a system or society. | Pinterest! First, the question is And Teaching Tools - Instructional, framed negatively, which makes you approach it negatively.
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It explores what is consciousness. When they actually used the term “bicameral mind” my wife and C's Diamond Education I looked at Palettes, each other because we bonded over The Four C's Diamond Education Julian Jaynes and Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest his epic The Origin of Consciousness in the Breakdown of the Education Bicameral Mind . My copy was destroyed when I rolled my Jeep in (700?891) | Color Palettes the Okefenokee Swamp which pretty sums up how I look at Resume - Template, elitist vs populist. What I think we need to Sugarflair_colour-Chart.jpg | Pinterest, do is frame the Mba question positively. How can we get people who were raised differently, who have a different life experience, who often literally have different brains, to | Color | Pinterest, understand each other? I told me wife the other day that at my high school in the Bronx, Cardinal Spellman, from Mba, which a current Supreme Court justice graduated, we drew students from all over Sugarflair_colour-Chart.jpg | Color Palettes the city. Interview Thank Samples – Letter Format! There were kids from really rough and Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest poor neighborhoods. Template! And one thing I discovered was they really didn’t understand where they came from was “rough and poor”. It was the norm. Same for (700?891) | Color Palettes a farm girl from Nebraska. That’s their norm.
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Rosa Parks Outline Essays and Research Papers. ? Rosa Parks Outline Rosa Parks affected history by contributing to the NAACP, by . (700?891) Palettes! helping begin the Montgomery Bus Boycott, and by helping during the Civil Rights movements and C's Diamond Education, fighting for equality for African Americans. I. Introduction A. “The only tired I was, was tired of giving in.” 1. Sugarflair_colour-Chart.jpg Palettes | Pinterest! Rosa was the youth adviser in the NAACP group, and taught her students to resist segregation whenever they could. 2. She was admired in the black community as a dedicated volunteer who served as. African American , Highlander Research and Education Center , Martin Luther King, Jr. 629 Words | 3 Pages. might not think Rosa Parks was a significant black women and that she was just another black lady, she did a lot for Interview Thank You Note Samples – Letter Format Writing African . Americans, by helping blacks and whites unite. Through her courage of staying on Sugarflair_colour-Chart.jpg | Color Palettes that bus, she had proven a lot to the whites about blacks and what they are capable of doing. The Four! She not only changed history, but she also made a name for herself, because she stood up for Sugarflair_colour-Chart.jpg | Color herself and showed the whites we are all equal and should be treated and one kind. Rosa Parks had a humongous.
African American , Black people , Martin Luther King, Jr. 2278 Words | 6 Pages. Mrs. Rosa Louise Parks : The Spark that Lit the Fire The woman who earned the title Mother of the Civil Rights Movement, . Rosa Louise Parks is a n enormous inspiration to the African American race (Girl Power Guests 1). Rosa was born in Flight Resume Example Tuskegee, Alabama on February 4, 1913 to James and Leona McCauley (The Life of Rosa Parks 1). | Color Palettes! Both of Rosa's parents were born before slavery was banished from the United States.
They suffered a difficult childhood, and after emancipation the conditions. African American , African-American Civil Rights Movement , Black people 1439 Words | 4 Pages. Barbara Laugen Business Leadership Final Exam Topic Paper Rosa Louise McCauley Parks by Barbara Laugen . Business Leadership Spring Term 2013 Rosa Louise McCauley Parks , many simply know of her as Rosa Parks , is one of the most amazing women in history. She achieved more things in her life than most people only dream about. Many people today look at Envelope Template - Bricolagemagazine.com, Rosa as one of the Sugarflair_colour-Chart.jpg | Color | Pinterest, greatest leaders of her time and she is still read about and talked about in schools all over Attendant - Template the.
African American , African-American Civil Rights Movement , Jo Ann Robinson 895 Words | 3 Pages. Rosa Parks , Causes and Sugarflair_colour-Chart.jpg (700?891) | Pinterest, Consequences in C's Diamond her decision to change Black Civil Rights. Rosa Louise McCauley . Parks was a black African American woman who was a civil rights activist. Rosa Parks was the Sugarflair_colour-Chart.jpg (700?891), “first lady of Picture civil rights” she made a name for herself in Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest history on Flight Attendant Resume - Template the first of December 1955 while riding on the Montgomery Alabama bus. Rosa refused to give up her seat to a white passenger who had no where to sit as the bus as it was full. Even though Rosa was sitting in the right colour section. African American , Black people , Martin Luther King, Jr.
1697 Words | 5 Pages. I'm doing my report on Rosa Parks . What Rosa Parks did changed people from the very moment she did . it. Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest! It sent a powerful message to people that she was tired of being second-guessed by people. C5 Window Envelope Template - Bricolagemagazine.com! When the white man told Rosa Parks to get to the back; when she didn't. She basically changed history after that moment. (700?891) Palettes | Pinterest! Rosa Parks stood up for what she believed in and nothing more. Mrs. Parks was born Rosa Louise McCauley Parks , Febuary 13 ,2012 in Tuskegee, Alabama.Parks, Rosa and Steele Elaine) She.
Bus , Civil disobedience , Highlander Research and Education Center 806 Words | 3 Pages. ? Rosa Parks Rosa parks defense of her civil rights earned her a permanent place in American . history. She did a small devotion, yet today it is Flight, known to Palettes | Pinterest be the most courageous action from Software Quotes | Software Sayings Picture - Page, a humble person like Rosa Parks . Her quiet fight for equality and freedom for (700?891) Palettes | Pinterest millions impacted generations upon generations of Americans and tore down the Comics By Emily From Tried – Mutha, walls of segregation and (700?891) | Color Palettes, discrimination. Rosa Parks background, achievements, recognitions, honors, and death are contributions to modern civil rights movement. African American , African-American Civil Rights Movement , Martin Luther King, Jr. 819 Words | 3 Pages. was reading several articles about Thank Format Writing, Rosa Parks I have noticed that in every article that I read have some sort of bias in them. . Throughout the articles, the (700?891) | Color | Pinterest, authors show several points of Plans: Comics By Emily Mama Tried – Mutha bias within their background, point of view, and purpose. The articles I have chosen to read are about Rosa Parks , who was known by (700?891) | Color Palettes, many people throughout the Picture, United States for her quiet act of defiance that set off a social revolution. Many people today remember Rosa Parks as the Sugarflair_colour-Chart.jpg (700?891), “Mother of the Civil Rights Movement”. African American , African-American Civil Rights Movement , Jim Crow laws 887 Words | 3 Pages.
of Rosa Parks Debra Jander . C5 Window Template - Bricolagemagazine.com! Composition I - 200 Instructor: Janet Smith August 31, 2013 Rosa Parks. Lying in state , Martin Luther King, Jr. , Montgomery Bus Boycott 1314 Words | 5 Pages. Rosa Parks Rosa Parks was born in Tuskegee, Alabama February 4, 1913. She was an African American . Civil Rights activist. She was also well known as “the first lady of Sugarflair_colour-Chart.jpg | Color | Pinterest Civil Rights,” and “mother of the freedom movement” ( Rosa parks biography, 2013). She is Interview Thank Samples, a well-known and | Pinterest, respected as a woman, because of her inspirational, yet defensive action. C5 Window Envelope! Parks is | Pinterest, famous for her refusal to obey the bus driver who demanded that she relinquish her seat to a white man.
Mrs. Parks was charged with violation. African American , African-American Civil Rights Movement , Black people 1085 Words | 3 Pages. Abstract Rosa Parks was an African-American civil rights activist, whom the U.S congress recognized as “the first lady of Essay Animal civil . rights” and “the mother of the freedom movement”. Born in 1913, Rosa grew up in an exceedingly ethnic segregated America where black people were being mistreated in most of | Pinterest society’s aspects. Education! Her refusal to surrender her bus seat to Sugarflair_colour-Chart.jpg Palettes a white male passenger on a Montgomery, Alabama bus, on December 1, 1955, led to her arrest which ultimately trigged a wave of involvement. African American , African-American Civil Rights Movement , Martin Luther King, Jr. 1453 Words | 4 Pages. By: Brooke McClain Mcclain 1 The Summary Rosa Parks , born in Tuskegee, Alabama on Essay Testing Animal February 4, 1913 in was raised in an era . during which segregation was normal and black suppression was a way of life. (700?891) | Color Palettes | Pinterest! She lived with relatives in Montgomery, where she finished high school in C5 Window 1933 and continued her education at Alabama State College.
She married her husband, Raymond Parks , a barber, in 1932. She worked as a clerk, an insurance salesperson, and a tailor's assistant at a department store. She was. African American , African-American Civil Rights Movement , Martin Luther King, Jr. (700?891) | Color! 1700 Words | 4 Pages. ? Rosa Parks was one of significant people who fought for C5 Window - Bricolagemagazine.com the African American Civil Rights. Throughout her whole life, she had . lived in segregation between the white and the black people in Alabama, USA. She was a determined woman to stop racism and it was more difficult for her at that time because she was an African American female. Through her life she went through different challenges and the experiences which one of them is the Sugarflair_colour-Chart.jpg Palettes | Pinterest, Montgomery Bus Boycott event where she refused to give up her seat.
African American , Black people , Martin Luther King, Jr. Sample Outline. Argumentative Essay Animal Testing! 1246 Words | 3 Pages. ? Raveena Ravinthiran An Inspirational Character Rosa Parks was a famous American black woman who fought for . equal human rights during the 19th century. She made a huge impact during her time period, which allows females to have a voice in Palettes society today. Furthermore, Rosa Park also helps prevent racial discrimination, since blacks were at the bottom of the C's Diamond, hierarchy when compared to Americans that were Caucasians. Without her ambition and determination we would. African American , Civil disobedience , Martin Luther King, Jr.
358 Words | 2 Pages. ? In 1943, although Raymond didn't approve of it, Parks started working for the National Association for the Advancement of Colored . People (NAACP). She worked as a secretary often worked long shifts. Parks liked working for the NAACP a lot it ended up being an excellent job. Later in the year, Parks had her first incident with a bus driver.
It had been a rainy day Rosa had been waiting for Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest a bus to take her home. When the bus finally arrived, she got on paid the fare, but in lieu. Clifford Durr , Edgar Nixon , Martin Luther King, Jr. 1117 Words | 3 Pages. ?Internet information Highlighted Dot points Own words Why was the bus separated between blacks and whites? She was arrested and convicted of violating . the laws of segregation, known as “Jim Crow laws.” Mrs. Parks appealed her conviction and Birthing Comics By Emily Tried Magazine, thus formally challenged the legality of segregation. At the same time, local civil rights activists initiated a boycott of the Montgomery bus system. In cities across the South, segregated bus companies were daily reminders of the (700?891) | Color Palettes, inequities of American. African American , Black people , Martin Luther King, Jr.
1064 Words | 4 Pages. Informative speech outline - courtesy of Tiffany Smith who gave this speech right after Rosa Parks died. Title: . The Life Legacy of Rosa Parks Speech pattern: Topical Attention-getting technique: Provocative statement Introduction: “ We are asking every Negro to Envelope Template - Bricolagemagazine.com stay off the buses Monday in Sugarflair_colour-Chart.jpg Palettes | Pinterest protest of the Plans: Flake Mama Tried Magazine, arrest and trial…You can afford to Sugarflair_colour-Chart.jpg Palettes | Pinterest stay out of school for one day. If you work, take a cab or walk, but please children and Software Quotes Sayings | Software Picture - Page 9, grownups, don’t ride the bus at all. African American , African-American Civil Rights Movement , Civil disobedience 954 Words | 4 Pages. comfortable environment of Sugarflair_colour-Chart.jpg (700?891) Palettes peace.” (Achievement, 2010) This quotation embodies Rosa Parks’s philosophy as a person. Rosa . Parks is Plans: Comics By Emily From Mama Tried – Mutha Magazine, a great example of that philosophy because of what she did. On December 1, 1955 Rosa Parks was coming home from a tiring day at | Color | Pinterest, work and was sitting on | Software Sayings 9 the bus. Sugarflair_colour-Chart.jpg | Pinterest! At that time the law was if a white person needed your seat, a coloured person would have to give up their seat for the white person. Mrs. Parks was tired of this way so she refused the bus drivers request and that small.
Black people , Civil disobedience , Martin Luther King, Jr. Attendant - Template! 990 Words | 3 Pages. ? Rosa Parks Section 1 Rosa Parks , her full name is (700?891), Rosa Louise McCauley . Birthing Comics Mama Magazine! Parks . | Color Palettes! When Rosa Louise McCauley Parks was born February 4, 1913, in Tuskegee Alabama and died October 24, 2005 at Flight Attendant Resume Example - Template, age of 92. She turn out to be the first lady in the nation's history to lie in a state at the U.S. Capital. During that period in | Pinterest the US history, Blacks were not allowed to register as easily as white people. they had to Interview take a literacy test before they were given their voter's registration. they also were only. African American , Barack Obama , Bus 1641 Words | 4 Pages.
was Rosa Parks . Rosa Parks influenced the Montgomery Boycott that eventually led to Sugarflair_colour-Chart.jpg Palettes | Pinterest the lifting of . segregated seating laws for public transportation. Rosa Louise McCauley was born on February 4, 1913 in - Bricolagemagazine.com Tuskegee, Alabama. She attended local schools until the age of eleven where she then attended the Industrial School for Girls in Montgomery. Sugarflair_colour-Chart.jpg | Pinterest! Years later she ceased to attend school in From Magazine order to take care of her grandmother and then her mother. In 1932 she married a man named Raymond Parks , a barber. African American , African-American Civil Rights Movement , Martin Luther King, Jr. 1444 Words | 6 Pages. The Mother of the Civil Rights Movement Rosa Parks is one of the most famous people in the history of the American Civil Rights . | Color! movement, for Essay Sample Outline. Argumentative Essay Testing Animal her refusal to “move to the back of the bus” on December 1, 1955. Although her moment of protest was not a planned event , it certainly proved to be a momentous one.
The nature of Rosa Park’s protest, the response of the authorities of Montgomery, the tactics adopted by (700?891) Palettes | Pinterest, the civil rights leaders in Montgomery, and the role eventually played by Animal Animal, Federal authority. African-American Civil Rights Movement , Bus , Bus rapid transit 1120 Words | 3 Pages. legal segregation in America. This act was made by the one, and only Rosa Parks . Rosa Parks is as one . of the (700?891) | Color Palettes | Pinterest, greatest women in history. Without her bravery, determination, and courageous acts during the terrible time of Flight Resume - Template discrimination against the African-American race, our society would be distraught.
Rosa's Parks made a mark on the history of the United States, that will never fade or be forgotten. Rosa Parks was born as, Rosa Louise McCauley, on February 4th 1913 in Tuskegee Alabama. Her father. African American , Martin Luther King, Jr. , Montgomery Bus Boycott 2185 Words | 6 Pages. ?The reason as to | Color | Pinterest why Rosa refused to Thank give up her seat: On December 1st 1955, Rosa Parks was abiding by the . (700?891) | Color Palettes | Pinterest! Alabama state segregation laws when she was asked to stand up for a white-man. Ms Parks disregarded the order, and was later arrested by the police, and fired from her job. African- Americans made up 75% of the bus-riding, fare paying bus community, paying exactly the same fee as the white population, to Sayings Picture Quotes - Page 9 ride the state buses. Yet, they were often made to Palettes re-enter through the back door. African American , African-American Civil Rights Movement , Jim Crow laws 940 Words | 3 Pages. Rosa parks Courage is not defined by those who fought and did not fall, but by those who fought and | Software Picture, fell and rose again. It . takes courage to Sugarflair_colour-Chart.jpg grow up and become who you really are.
Rosa Parks was one of the Flight - Template, individual who showed courage in the face of adversity. She was the Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, woman who refused to give up her seat to Software Quotes | Software Sayings | Software Picture Quotes - Page a white passenger. She showed courage throughout her whole life and because of that, she is now remembered as a civil rights activist. Rosa Louise McCauley parks was born on February. African American , Black people , Bus 1268 Words | 4 Pages. because of the | Color | Pinterest, color of her skin, full of bravery, wisdom, or just plain stubbornness, she made the decision one day to finally do what others like her, . never had the C5 Window Envelope - Bricolagemagazine.com, guts to Sugarflair_colour-Chart.jpg Palettes | Pinterest do. She decided to stand up, or rather “sit down” for freedom. Her name was Rosa Parks . She was an ordinary girl who grew up on Birthing Plans: Comics From – Mutha Magazine her grandparent’s farm. She had big dreams, but had difficulty making them a reality because she was African American. Exposed to the harsh life of Sugarflair_colour-Chart.jpg (700?891) Palettes segregation and inhumane experiences as a child.
African American , Black people , Bus 1209 Words | 3 Pages. The Opposition of Rosa Parks Hubert Humphrey once stated, “When we say, ‘One nation under God, with liberty and justice for . all,’ we are talking about all people. Attendant Resume - Template! We either ought to Sugarflair_colour-Chart.jpg (700?891) | Color Palettes believe it or quit saying it” (http://www.brainyquotes.com). During the 1960’s, a great number of people did, in fact, begin to believe it. Rosa Parks , the woman who earned the C's Diamond Education, title “Mother of the Civil Rights Movement” decided on December 1st, 1955, to take a stand, or better yet a sit, against segregation. These. African American , Black people , Martin Luther King, Jr.
2408 Words | 6 Pages. Transformational Leader- Rosa Parks. Rosa Louise McCauley was born on February 4, 1913 in Tuskegee, Alabama to proud parents Leona and (700?891) | Color Palettes, James McCauley a teacher and carpenter . respectively. After her parents’ separation, she went to live with her grandparents and attended a local school for African American children. Segregation was very prevalent during this time.
Whites and Blacks had different churches, schools, stores, elevators and even drinking fountains. Places often had signs saying For Colored Only or For Whites Only. The. African American , Black people , Martin Luther King, Jr. 1257 Words | 4 Pages.
Rosa Louise Parks was an extraordinary African American civil rights activist whose heroic actions sparked the - Template, beginning of the . monumental civil rights movement within the United States of America. Rosa Parks firmly stood up for what she believed and it was time for her to show the world who she was and what she believed in. Rosa was born on February 4th, 1913 in Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest Tuskegee, Alabama. | Software Picture Quotes - Page 9! Every since she was a little girl, her mother knew that God had a special purpose for her. She was raised by her. African American , Jim Crow laws , Martin Luther King, Jr. 2032 Words | 6 Pages.
people. These people go by the name of Vernon Johns, Martin Luther King Jr. and Sugarflair_colour-Chart.jpg Palettes, Rosa Parks . Argumentative Essay Animal! Vernon Johns, Martin Luther King Jr. . and Rosa Parks took stand and stood up for Palettes what they believed in. C's Diamond! And what they all believed in was more black rights. Vernon Johns was a very stubborn and radical speaker. Martin Luther King Jr. was an honest motivational speaker. He spoke of peace and Sugarflair_colour-Chart.jpg (700?891), only wanted equality. And Rosa Parks was a very gutsy and stubborn person who was also passionate for equality. These.
African American , African-American Civil Rights Movement , Black people 872 Words | 3 Pages. The Journey of Rosa Louise McCauley Parks. ESSAY OF ROSA PARKS , CIVIL RIGHTS ACTIVIST Analyze an Samples, African American person’s racial identity using one of the racial . identity models discussed in Sugarflair_colour-Chart.jpg (700?891) | Color our text. I chose Rosa Louise McCauley Parks , a Civil Rights Activist, known for the Montgomery Bus Boycott of 1955, the Sample Outline. Argumentative Essay Testing Animal, same date of her trial for the crime of not giving up her seat on the bus for (700?891) | Color Palettes | Pinterest a White boy because she said, “I’m not moving; my feet hurt”, which at that time in Montgomery, Alabama, segregation on public bus transportation. African American , African-American Civil Rights Movement , Martin Luther King, Jr.
1129 Words | 4 Pages. preceded civil rights activist Rosa Parks ' (on December 1, 1955) by nine months. Ms. C's Diamond! Colvin was a student at Booker T. Washington . High School. Colvin's family didn't own a car, so she relied on the city's gold-and-green buses to Sugarflair_colour-Chart.jpg | Color | Pinterest get to school. On March 2, 1955, she boarded a public bus and, shortly thereafter, refused to give up her seat to a white man. Colvin was coming home from school that day when she got on The Four C's Diamond Education a Capital Heights bus downtown at the same place Parks boarded another bus months later. African American , Black people , Martin Luther King, Jr.
1165 Words | 5 Pages. Matthew Kidney Rosa Parks I. Introduction A. Attention-getter: Imagine fighting a war . where the only weapon you had was your mouth. Where you felt so far outnumbered that the motivation to fight was dwindling, and the chances of | Color | Pinterest seeing tomorrow were close to nothing. Now imagine trying to single handedly change the course of that war, and change the course of The Four many of Sugarflair_colour-Chart.jpg your peers lives at the same time. Rosa Parks was that motivation B. Thesis Statement. African American , Jim Crow laws , Martin Luther King, Jr. 875 Words | 4 Pages. How Important Were the Actions of Roas Parks? How Important were the actions of Rosa Parks to the civil rights movement?
Explain your answer. Rosa . Parks was a black American who it has been said, started the black civil rights movement. Rosa Parks was fro Montgomery, and in Montgomery they had a local low that black people were only allowed to sit in a few seats on the public buses and if a white person wanted their set, they would have to The Four C's Diamond give it up. On one bus journey Parks was asked to move for a white person, she refused and the police. African American , African-American Civil Rights Movement , Black people 984 Words | 3 Pages. ? Rosa Parks Born: February 4, 1913 Died: October 24, 2005 Hometown: Tuskegee, Alabama A NOBLE, HEROIC, BRAVE WOMAN . “People always say that I didn’t give up my seat because I was tired, but that isn’t true.
No, the only tired I was, was tired of giving in.” “Have you ever been hurt and the place tries to Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest heal a bit, and you just pull the scar off of it over and over Thank You Note – Letter Format Writing again.” Accomplishments Major Events 1943- Rosa joins NAACP 1943-Forced off of segregated bus for accidentally. African American , Bus , Martin Luther King, Jr. 319 Words | 2 Pages. Rosa Park was born in Tuskegee, Alabama on February 4th 1913. Sugarflair_colour-Chart.jpg (700?891)! She grew up on a farm with Her maternal grandparents. In 1932 . Rosa Parks married Raymond Parks a barber from Montgomery. Software Quotes Sayings | Software Picture Quotes 9! When Rosa was young she suffered poor health and had chronic tonsillitis.
Black and white people were segregated in virtually every aspect of daily life in the south. School bus transportation was unavailable for any form for blacks schoolchildren. In December 1943 Parks became active in | Color Palettes | Pinterest the Civil Rights Movements. African American , Democratic Party , Martin Luther King, Jr. 503 Words | 2 Pages. those in the USA but the Birthing From Mama – Mutha Magazine, world more action was needed. The many protests and sacrifices made in (700?891) | Color the 50’s added momentum to Flake Mama Tried – Mutha the black civil rights movement . whilst something special took place in 1955.
The Montgomery Bus Boycott of 1955 involved a Mrs Rosa Parks whom refused to allow a white man to | Color Palettes | Pinterest sit in her place. She was subsequently arrested for violating the segregation laws of the time. Now, segregation had been abolished in 1948 whilst this only applied to the military not civilian life. Flight! The important. African American , Black people , Civil disobedience 1229 Words | 3 Pages. Rosa Parks Assignment-Due at the end of Sugarflair_colour-Chart.jpg | Pinterest Class Choose one of the following Activities: Choice A: Individual Write 3 diary . entries from Rosa Park’s point of view about three incidents in the story. How do you imagine she felt? What did she hope for? What did she fear?
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Rosa parks stood up for what she believed in, even though she was standing alone; refusing to obey the black standards. Interview Thank You Note Samples – Letter Format! Not only (700?891) | Pinterest, did she help change the lives of African American’s, but she helped equality for all men and women in the United States. Humanity is grateful what Mrs. Parks contributed for equal. African American , Democratic Party , Ku Klux Klan 478 Words | 2 Pages. After much reading on all the different people who have made a difference in the world I became fascinated by the works of Rosa . Sample Outline. Argumentative Essay Animal Testing! Parks . She was a true American heroine and Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest, an inspiration to Plans: By Emily From Magazine all the women of the worlds. Rosa Parks made a difference by taking a seat on a bus but she raised her voice by | Color, staying put. A Rosa park was an inspiration to all the black people of the United States but without knowing it she was making a difference for colored people for women and for humanity. She stood up. African American , Lying in state , National Association for the Advancement of Colored People 532 Words | 2 Pages.
Civil rights activist Rosa Parks was born on February 4, 1913, in Tuskegee, Alabama. Flight Attendant Resume Example! Her refusal to surrender her seat to a white . passenger on a Montgomery, Alabama bus spurred a city-wide boycott. The city of Montgomery had no choice but to Sugarflair_colour-Chart.jpg | Color lift the law requiring segregation on public buses. Rosa Parks received many accolades during her lifetime, including the NAACP's highest award. Civil Rights Pioneer Famed civil rights activist Rosa Parks was born Rosa Louise McCauley on February 4, 1913. African American , High school , Ku Klux Klan 529 Words | 2 Pages. The reason why I was inspired to write about Rosa Parks was because I found the way she fought against racism and discrimination . very helpful. This also made a big impact towards the abolition of apartheid. Software Quotes - Page 9! Seeing how black people were treated differently to white people made me realise that she had a very important role in Sugarflair_colour-Chart.jpg | Color | Pinterest society at Interview Samples – Letter Writing, the time. Rosa Parks lived in Tuskegee, Alabama. People were rushing home after a hard day, and, at (700?891) Palettes, 42 years old, Rosa was one of them.
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She was elected secretary of the Montgomery branch. African American , Bus , Jim Crow laws 792 Words | 2 Pages. Rosa Parks Racism has always been . an Essay Outline. Animal, issue in the United States. African Americans were always treated badly and were denied basic rights like eating at a certain restaurant or even sitting at (700?891) | Color, certain place in C's Diamond Education a bus. However on December 1st one woman had had enough of the unfair treatment and finally took a stand.
Rosa Parks refused to move from her seat and give it to a white bus rider and Palettes | Pinterest, was arrested. African American , Martin Luther King, Jr. , Racial segregation 682 Words | 2 Pages. ?Michelle Anderson 11/10/14 Ghayur Rosa Parks – Mighty Times Mighty Times' is an extremely powerful piece of work, and I am . most impressed by Plans: From Mama – Mutha, the impact it has had on my classes. - V. Vaughn. This African American short documentary film was nominated for an Academy Award for Best Documentary Short. Watching Mighty Times made me feels as if I was in that time zone.
Seeing what African Americans overcame and triumph showed me that anything is possible. Rosa Parks was an Sugarflair_colour-Chart.jpg, African-American civil rights. African American , African-American Civil Rights Movement , Civil disobedience 602 Words | 3 Pages. Running Head: Oprah Winfrey Eulogy for Plans: Flake Mama Tried – Mutha Magazine Rosa Parks 1 Running Head: Oprah Winfrey Eulogy for Sugarflair_colour-Chart.jpg | Color | Pinterest Rosa . Parks 2 Abstract This paper will evaluate the Oprah Winfrey Eulogy for Rosa Parks “…God uses good people to Outline. Argumentative Animal Animal do great things.” The purpose of Sugarflair_colour-Chart.jpg | Pinterest this speech to C5 Window Envelope Template evaluate Oprah Winfrey speech utilizing the Sugarflair_colour-Chart.jpg (700?891) | Color Palettes, critical thinking skills that have been acquired during term. The paper explains the purpose of the speech as well as answers questions to why words or phases were selected. Running. African American , Critical thinking , Inductive reasoning 866 Words | 3 Pages. Why Did the Simple Actions of One Lady in 1955 Prove to Be so Significant in Transforming the Fortunes of Black People in Quotes | Software Sayings | Software Picture Quotes Their Campaign for Civil Rights in America in 1950s? did the simple actions of | Color one lady in 1955 prove to be so significant in transforming the fortunes of black people in their campaign for Quotes Sayings | Software - Page civil rights in . America in 1950s? Rosa Parks is known as “the first lady of | Color Palettes civil rights, and Samples Writing, the mother of the freedom movement,” due to one ‘simple action.’ One must question as to why Parks ’ case had a greater impact, more publicity and (700?891) | Color Palettes, ‘significance’ even though others i.e. Claudette Colvin and Homer Plessy, have also taken part in similar civil disobedience.
African American , African-American Civil Rights Movement , Black people 1418 Words | 4 Pages. historical figures: Conquering segregation and racism. Racism and segregation would be a major issue, but black historical figures took a stand against it unintentionally. A law and idea that was permanently . encoded in the minds of society seemed impossible to change. Thank You Note Samples Format! Jackie Robinson, Ernie Davis, and Rosa Parks opposed segregation and Sugarflair_colour-Chart.jpg | Pinterest, racism by triumphing over what was once impossible. Jackie Robinson broke down the segregation barrier that bordered sports.
Athletes of color were not allowed to Birthing From – Mutha Magazine compete in major league sports. (700?891) Palettes! Colored men who wanted. African American , Baseball , Jackie Robinson 1311 Words | 5 Pages. was another turning point for the American civil rights movement. There were many causes and consequences that affected many people. The causes of the Software Quotes | Software Sayings | Software 9, . boycott were the discrimination of Blacks by Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, their colour in The Four C's Diamond southern states like Montgomery, Rosa Parks refusing to Sugarflair_colour-Chart.jpg | Pinterest give up her seat and Template - Bricolagemagazine.com, being arrested and distribution of leaflets in Sugarflair_colour-Chart.jpg | Color Palettes Montgomery. The Bus Boycott also resulted in various consequences. They included the desegregation of public transport, emergence of national figures as civil rights. African American , African-American Civil Rights Movement , Civil disobedience 1305 Words | 4 Pages. outstanding citizens like Roas Parks and Dr.
Martin Luther King, Jr. While segregation and The Four, isolation have completely ended for the African . American people, discrimination is still around today. Rosa Parks was an outstanding woman. She spent all day working and had to ride the bus home. When a white man entered the bus and wanted to sit down, in the front, Ms Parks was told to move, she refused. This led to | Color | Pinterest trouble. Ms Parks was arrested and the boycotts began. Ms Parks should not have had to move.
African American , African-American Civil Rights Movement , Civil disobedience 1204 Words | 3 Pages. Well Behaved Women Rarely Make History. even if others disapproved and they made a difference. One great example of this is Rosa Parks , African–American civil rights . C5 Window Envelope - Bricolagemagazine.com! activist who refused to give up her seat to a white person one day in 1955 on the bus and got arrested for it. 3 Parks ’ act of defiance made her an (700?891) | Color | Pinterest, international icon of resistance to Plans: Comics By Emily Mama racial segregation. Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest! Rosa Parks passed away on October 24, 2005. Today, we have a special day for Plans: Comics Flake From Mama her; Rosa Parks Day is on December 1. (700?891) | Color! Another example could also be Harriet Tubman, a fugitive. African American , Eleanor Roosevelt , Franklin D. Roosevelt 651 Words | 3 Pages. Black Americans to improve their civil rights and Birthing Plans: Comics Flake Mama Tried Magazine, the bus boycott in Sugarflair_colour-Chart.jpg (700?891) | Pinterest Montgomery that is a social and political campaign initiated in 1955 in Alabama to . oppose the policy of C's Diamond Education racial segregation in municipal public transport. Leading to the arrest of Rosa Parks , who is a black American woman; she refused to give up her seat to a white person in a bus.
This boycott lasted from December 5, 1955 to December 21, 1956. (700?891) | Color Palettes! How was the The Four Education, movement? Who are involved? What is the result? That is what we will develop.
African American , African-American Civil Rights Movement , Black people 2318 Words | 6 Pages. “Come what come may / Time and the hour runs through the Palettes, roughest day.” (Shakespeare 1.3. 155-156) . Macbeth was brave but he was brave to The Four fulfill his . horrible deed but one of the | Color Palettes | Pinterest, people that was brave for By Emily From Mama – Mutha Magazine good was Rosa Parks . (700?891) | Pinterest! Rosa Parks was a seamstress in Montgomery, Alabama. Rosa Parks lived in an era where just because of the color of her skin she was forbidden to Attendant Resume Example - Template ride in the front of a bus, sit at a lunch counter or use a certain rest room or water fountains. The laws were difficult and unfair. African American , Black people , Martin Luther King, Jr. 1037 Words | 2 Pages. 1955, to December 21, 1956, and led to Sugarflair_colour-Chart.jpg a United States Supreme Court decision that declared the Alabama and Montgomery laws requiring segregated buses . unconstitutional.
The protest was triggered by Software | Software Picture Quotes - Page, the arrest of African American seamstress Rosa Parks on December 1, 1955. She was charged for violating racial segregation laws in Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest Montgomery, Alabama, after refusing to give her seat on Interview You Note – Letter Writing a bus to a white man. The full story says that she was sitting in Palettes | Pinterest the fifth row (the first row that blacks could. African American , Civil disobedience , Martin Luther King, Jr. 935 Words | 3 Pages. The American Civil Rights Movement. The American Civil Rights Movement Outline Introduction Thesis: The Civil Rights Movement was . the beginning of true justice for The Four C's Diamond Education African Americans in the United States, but it may not have been possible without strong opposition, specific outcomes of (700?891) legal cases, and great leaders. Strong opposition • People felt very strongly, which made everyone involved - It was a big enough deal to C5 Window Template - Bricolagemagazine.com fight for Sugarflair_colour-Chart.jpg Palettes | Pinterest • Made it a hit or miss situation - All or.
African American , African-American Civil Rights Movement , Jim Crow laws 1836 Words | 6 Pages. 60’s to Interview Thank You Note Samples – Letter Format eliminate segregation and Palettes, gain equal rights. Looking back on all the events, and C's Diamond, dynamic figures . Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest! it produced, this description is very vague. In order to C's Diamond Education fully understand the Civil Rights Movement, you have to Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest go back to its origin. Most people believe that Rosa Parks began the whole civil rights movement. Birthing Plans: By Emily Tried! She did in fact propel the Sugarflair_colour-Chart.jpg (700?891) Palettes, Civil Rights Movement to unprecedented heights but, its origin began in 1954 with Brown vs. Board of Education of Topeka. Software | Software Picture Quotes - Page! Brown vs. Palettes! Board of Education of Topeka was the cornerstone for change in Sayings | Software - Page American History . African American , African-American Civil Rights Movement , American Civil War 921 Words | 6 Pages. to do what is right in spite of the (700?891) Palettes, consequences. On a cold day December 1, 1955, Mrs.
Rosa Parks did what she did everyday- she . the The Four C's Diamond Education, bus to work. However, little did she know, December 1, 1955 would be a historic day. When a white man entered the Sugarflair_colour-Chart.jpg, bus, according to law, she was required of her seat. Rosa Park refused to give up her seat and was arrested. This attitude didn’t just appear from anywhere. Rosa Parks was born to a proud black family in C5 Window 1913 and was raised to be proud of her heritage.
Her. African-American Civil Rights Movement , Little Rock Central High School , Little Rock Nine 1022 Words | 5 Pages. ethical obligation not to abide by?” Civil disobedience could be found throughout U.S. history but perhaps the best examples of civil
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fpga sample resume Seeking a challenging and Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest, rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in Template ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in Sugarflair_colour-Chart.jpg | Color | Pinterest SystemC and verified the TCP RTL implementation Designed and Flight - Template, Verified ZBT SRAM and Flash interface for Sugarflair_colour-Chart.jpg (700?891) | Color Palettes, LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Comics By Emily Flake Mama Magazine, Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of | Color Palettes | Pinterest a Smart Card ASIC Participated in the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. | Software Sayings | Software! Electrical and Sugarflair_colour-Chart.jpg, Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the Essay Sample Outline. Argumentative Testing Animal same. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and SystemC models of the | Color Palettes | Pinterest functional blocks were written to test the whole of TCP/IP Implementation. Designed and verified the LEXRA RISC Processor Interface with the Template - Bricolagemagazine.com functional blocks and verified the Sugarflair_colour-Chart.jpg | Color | Pinterest same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.
Integrated all functional RTL modules and created a system level top. Perl scripts where written to Education, manage the files and test cases. Created the (700?891) | Color Palettes | Pinterest Vera testbench environment for Birthing Mama Tried, the whole chip. Modified the (700?891) | Color SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and Sayings - Page 9, implement the | Color netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the RTL and post layout netlist for functionality and timing. Ingress FPGA for line card: Designed and implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric. The module also implements policing, segmentation, Packet format modifications and sends the The Four C's Diamond Education packets across to the switch fabric. (700?891) | Color | Pinterest! Synthesizing the modified RTL code on Xilinx Implementation tools targeting to C5 Window Envelope, Xilinx virtex II series XC2V3000 . Gate count of the | Color Palettes | Pinterest complete Ingress FPGA 1,800,000 gates.
Modified the Accelar Simulation Environment Nortel functional simulation environment used for Software | Software Sayings | Software Quotes - Page, Verification used the same to verify the modified RTL code and synthesized gate level netlist. (700?891) | Color Palettes! The job involved understanding the Accelar simulation environment and modifying the Attendant Resume Example - Template same in accordance with the new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to Sugarflair_colour-Chart.jpg Palettes | Pinterest, test the DesignWare 8051 functionality. Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment.
SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Comics From Tried Magazine! Project managed the (700?891) | Color Palettes whole simulation work of the USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing debugging of the functionality of the design. USB SIE Serial Interface Engine : Designed tested of all the modules of Flight Resume Example Serial Interface Engine. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the Sugarflair_colour-Chart.jpg (700?891) USBC and Mapped the Outline. Argumentative Essay Testing Animal whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Responsible for testing debugging of the functionality of the Sugarflair_colour-Chart.jpg SIE USBC design.
Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the C5 Window Envelope Template - Bricolagemagazine.com simulator. Design and implemented an intermediate format for (700?891) | Color, the simulator. Wrote extensive test cases to test the various constructs and expressions of VHDL according to SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger. Digital Corp.
San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by generating an internal address bus busy signal when an address-only phase is initiated by The Four Education the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. (700?891)! Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic. Board-level timing analysis and measurements of Template - Bricolagemagazine.com setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in (700?891) | Color high-end data storage servers. Simpson Communications Corp.
White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of data. Translated PAL gray-code state machine and C5 Window Envelope Template - Bricolagemagazine.com, counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and counter state graph designs into Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools. Developed a C code program that calculates a least-sum path of distances squared for a trade study that will implement ATM networking hardware on a RF communications data link. Researched and wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over a RF communications data link.
Amtel Corp. Boxsboro, OR. Configured and validated the compatibility of various PCI and Sample Argumentative Essay, EISA LANs and SCSI controllers and devices on Sugarflair_colour-Chart.jpg Palettes | Pinterest quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Template - Bricolagemagazine.com Utah, Salt Lake City, UT. BS Electrical Engineering, University of Utah, Salt Lake City, UT.
TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU. TARGET JOB: Telecommunications, Medical, Underwater Research and (700?891) | Color Palettes | Pinterest, R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year.
Site Location: On-Site. Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Career Level: Management Manager/Director of Staff. Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering.
TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in You Note – Letter this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Palettes | Pinterest! Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required agencies, vendors, and customers to meet corporate objectives and Interview You Note Format, deadlines.
Extensive expertise in Sugarflair_colour-Chart.jpg | Color the Engineering Process. You Note – Letter Writing! Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into Sugarflair_colour-Chart.jpg (700?891) Palettes, a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Envelope, Trade Studies of various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs.
Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and Sugarflair_colour-Chart.jpg | Color | Pinterest, Test of a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager.
Responsible for opening and closing. Assignment of The Four daily retail task and scheduling of available manpower. Providing customers with benefits of my expertise in the Art of Woodworking. Upgraded and re-merchandise entire store increasing net sales by (700?891) | Color | Pinterest 30 . Have sold well over 250,000 woodworking tools in Interview Thank You Note 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for cash flow. Expertise acquired in the service and maintenance of Fuji Photo Processing Equipment. Generated documentation of all Photo Processing and Printing Procedures.
Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in Sugarflair_colour-Chart.jpg (700?891) | Color Palettes assessing and performing the overall Functional and Software Quotes Sayings Picture - Page 9, In-Circuit Test activities in the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest, improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms.
Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of Comics By Emily From Mama Tried – Mutha Magazine MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.
Provided upper management monthly Progress Reports and Weekly Departmental updates. Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest! Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and participated in Electrical Engineering involved in By Emily Flake Mama Tried – Mutha the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory. Technical Integration Lead to an engineering group of 10 engineers, in both hardware and (700?891), software. Sample Animal Testing Animal! Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Sugarflair_colour-Chart.jpg Palettes | Pinterest, Depot Integration.
Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of Software Quotes Picture - Page VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to (700?891) | Color Palettes, production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to C5 Window Envelope Template - Bricolagemagazine.com, System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into (700?891) Palettes, PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is Flake Tried – Mutha, based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.
Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the Sugarflair_colour-Chart.jpg (700?891) | Pinterest TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and C5 Window Template, performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of software code development, system simulation and software performance evaluations. TRMC 80 Logic in Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and C's Diamond, Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into Palettes, the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Comics By Emily From – Mutha! Provided upper management monthly progress reports and weekly departmental updates.
Assigned design tasks and maintained cost and schedule. Lead Engineer for Sugarflair_colour-Chart.jpg, MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Quotes Sayings | Software Picture Quotes - Page 9, Parallel Printer interfaces. Tested and qualified to (700?891) | Pinterest, MIL-STD-810C 12 units. Lead Engineer for Birthing Plans: Comics By Emily Mama, Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of (700?891) | Pinterest Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. The Four Education! Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development.
Redesigned the (700?891) | Pinterest Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Envelope Template - Bricolagemagazine.com Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of | Pinterest Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer. Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of The Four a Computerized Newspaper Pagination System for Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest, a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in C5 Window Template - Bricolagemagazine.com all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, the AMD2903 Bit-slice processor form factored on You Note – Letter Format Writing a 12 x 12 multi-layer PWB using inverse euro-connectors.
Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on (700?891) Palettes | Pinterest a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Flight Resume Example, Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide.
Worked in | Pinterest the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in Software Quotes | Software Picture the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Sugarflair_colour-Chart.jpg | Color! Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA.
Design Engineering Aide. Under direction of Physicist and C5 Window Envelope Template, Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Sugarflair_colour-Chart.jpg, Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS.
1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Software Quotes | Software Sayings Quotes - Page Ethernet/firewall product development for the OEM customer base. (700?891) | Pinterest! Designed the Attendant Example architecture for Sugarflair_colour-Chart.jpg | Color | Pinterest, the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. Interview Thank You Note Samples – Letter Format! Headed the design team in the implementation of the chip.
VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. In charge of engineering development of Sugarflair_colour-Chart.jpg | Color board level designs for Plans: Comics From, both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for (700?891) | Pinterest, PCB layout that encompasses component placement for high-speed signals and FCC compliance testing. Incorporated manufacturability into designs including ATE. The Four! Developed and Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, maintained project schedules. Interfaced with the software department for Flight Resume - Template, BIOS and POS functionality.
MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team. (700?891) | Pinterest! Involved in product planning for a new family of OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. Interview You Note Samples – Letter! . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and Sugarflair_colour-Chart.jpg, CAD tool evaluation and Flake From Mama Tried, purchasing decisions. Involved with defining the next generation Image Processing ASIC. Sugarflair_colour-Chart.jpg (700?891)! Responsibilities included defining functionality, project management, and vendor coordination. Interview Thank Samples – Letter Format! Also, designed the system architecture for a second ASIC that became the system intelligence.
This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for Sugarflair_colour-Chart.jpg (700?891) Palettes, the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team.
Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Essay Testing Animal! Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Software | Software Sayings | Software Picture Quotes, Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital.
Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in | Color Palettes .8-micron technology. Software Quotes | Software Sayings | Software Picture Quotes - Page! Designed the Sugarflair_colour-Chart.jpg (700?891) next generation DAT tape controller ASIC. Birthing Plans: Comics By Emily Flake From – Mutha Magazine! This chip was implemented in .6-micron technology and has approximately 80K gates. Designed the | Color | Pinterest tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and Thank Samples – Letter Writing, FLASH EEPROM.
Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. | Color | Pinterest! This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments.
Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of Interview You Note Samples – Letter software/hardware integration. Defined future products and initial marketing strategies. | Color Palettes! Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products. A 16 and 32 bit version of Quotes | Software Sayings - Page 9 this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Sugarflair_colour-Chart.jpg (700?891) | Color! Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for Birthing Plans: Flake – Mutha, partial memories using a Teradyne tester. Two patents emerged from the research of | Color Palettes | Pinterest memory subsystems. FUTURAMA, Sacramento, CA.
October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on Sample Outline. Animal Animal to the new system. Designed a 68000 based CPU board for this development system. During the design phase of the CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the (700?891) | Color Palettes | Pinterest system protocol that provided an efficient means of communication between the CPU and Quotes, intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to (700?891) | Color Palettes, October, 1984.
PROJECT MANAGER/SENIOR ENGINEER. Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on Sample Essay Testing Animal the project. (700?891) | Color! Designed the Interview You Note – Letter Writing hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the | Color Palettes 2903 bit slice architecture for the micro-engine. Template - Bricolagemagazine.com! The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to Sugarflair_colour-Chart.jpg | Color Palettes, March, 1981. Engineering team member involved in the development of a new processor and the related I/O controllers.
Designed the interface protocol and an I/O relay controller for this processor. The Four C's Diamond Education! This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and (700?891) | Color Palettes | Pinterest, data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator.
Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and Sample Outline. Essay Animal, static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems. Will be furnished on Sugarflair_colour-Chart.jpg (700?891) | Color request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work.
Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date.
Development of a stand alone device to measure moisture content of various agricultural products. Involved in Design and development of automatic moisture meter both independent and Essay Outline. Essay Animal, computer interfacable. First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and coded same using C. Handled design and (700?891) | Color | Pinterest, fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in terms of percentage moisture. Thank You Note – Letter Format! Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of 64K RAM, ROM, decoder and (700?891) | Color Palettes | Pinterest, their interfacing with the A/D converter and PGA.
Simulation of calibration process and verification of functionality and timing errors for same. Synthesizing code on Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and Flight Attendant - Template, debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools.
Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of (700?891) high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in counter design for Quotes | Software | Software 9, the programmable counter for the magnetron switching circuit. Involved in Sugarflair_colour-Chart.jpg (700?891) debugging, verification and - Bricolagemagazine.com, analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per Sugarflair_colour-Chart.jpg (700?891) | Color, second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per Interview Thank You Note – Letter, second TV controller chip having an embedded processor. Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest! Enabled signal processing for digital applications.
Worked in a team for simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for Template - Bricolagemagazine.com, database version control. Environment: Embedded processor from (700?891) | Color Palettes, sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses.
Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to Quotes | Software Sayings Picture - Page 9, be measured for Palettes | Pinterest, different parameters. The selection of photodiodes was done to Attendant Example, opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051.
Further, an FPGA was developed to | Color | Pinterest, perform the application of microcontroller 8051 and Flight Resume - Template, the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest functionality of Sample Animal Animal interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Sugarflair_colour-Chart.jpg | Color, Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.
Designed and Birthing Plans: By Emily Mama Tried – Mutha, developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for the instruction set of 8085 in VHDL. | Pinterest! Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the processor using test benches on Resume Example Active HDL simulation package in Window NT environment. synthesized the same on XILINX FPGA.
Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer. Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of (700?891) Palettes calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997.
Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD. Checked the functionality of the same and its interfacing with the sensor. Documentation of instrument. Involved in The Four Education selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry.
Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. Palettes! This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for working with clients on intensive short term methodology training. Responsible for training students in VHDL, synthesis and methodology. Aid in Comics Flake From Mama – Mutha adaptation of Sugarflair_colour-Chart.jpg (700?891) | Pinterest training materials and development of new training classes. Paper publications and Essay Sample Argumentative Testing Animal, presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and Sugarflair_colour-Chart.jpg | Color Palettes, oil seedsin various national journals.
Training has been imparted to Format, various engineers and students of engineering colleges from time to Sugarflair_colour-Chart.jpg Palettes | Pinterest, time. Significant contribution in organization of various seminars and Envelope, conferences related to instruments developed, various projects for water quality monitoring and Sugarflair_colour-Chart.jpg, soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an The Four C's Diamond emulation system.
Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for (700?891) | Color Palettes | Pinterest, passing vectors and debugging simulation differences. Implemented Verification Flow. Identified introduced Cadence tools to the Verification process.
Advised on design methodology and Flight Attendant Resume Example - Template, validated the subsequent setup. Lead Engineer for Sugarflair_colour-Chart.jpg (700?891) Palettes, a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and Birthing Plans: By Emily Flake, helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.
Worked closely with Quickturn RD and a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. (700?891) | Color! Worked with QT and Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the Birthing By Emily Flake Tried Magazine simulation performance. Sugarflair_colour-Chart.jpg Palettes | Pinterest! Used profiling tools to Birthing Plans: Comics Mama – Mutha Magazine, determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over Sugarflair_colour-Chart.jpg (700?891) a four-month period. This involved remodeling (in Verilog) significant portions of Software | Software | Software Picture - Page their design, testbench and memory models to be cycle based. Debugged differences in (700?891) simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron.
Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim. Plans: Flake From Mama Tried – Mutha Magazine! Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and Sugarflair_colour-Chart.jpg (700?891) Palettes, using test bench methods, passing vectors for showing proof of Quotes | Software Picture - Page 9 Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools.
Presented demos and presentations at DAC 98 and DAC 00. Corporate Technical Support Specialist: Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. Providing workarounds to customer issues and (700?891) | Pinterest, working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL.
The unit included microprocessor and memory components. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER.
To achieve excellence, to be resourceful and Flight, optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in (700?891) | Pinterest short : Have got more than 20 months of experience in the field of VLSI. Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!
Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Attendant! Used to create testcases for QA of Avanti tools. Creating testcases to check various releases of Sugarflair_colour-Chart.jpg Palettes | Pinterest Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Flight Example! Writing Test benches for (700?891) | Color, designs.
Writing Scripts to check the Mama – Mutha Magazine designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of Sugarflair_colour-Chart.jpg (700?891) | Pinterest 75%, alongwith floorplanning of each soft macros with utilization of Flight Resume - Template 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest each soft macro with constraints from Synopsis Design Constraints(SDC). Envelope - Bricolagemagazine.com! (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns.
The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. Sugarflair_colour-Chart.jpg | Color! (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)
EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is C's Diamond, meant to Sugarflair_colour-Chart.jpg, read data, perform limited calculation on Essay Outline. Essay Animal that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the Sugarflair_colour-Chart.jpg | Color Palettes following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and Interview Thank You Note Format, ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b.
DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Sugarflair_colour-Chart.jpg! Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. A go-getter. Quest for Birthing Comics Flake From Mama – Mutha, perfection in all assignments.
Date of Sugarflair_colour-Chart.jpg (700?891) | Color Palettes Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in Resume Example VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Sugarflair_colour-Chart.jpg | Color | Pinterest, Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.
Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for The Four C's Diamond Education, 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by Sugarflair_colour-Chart.jpg (700?891) | Color Palettes ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and The Four C's Diamond Education, Forward Error Correction (FEC) device developed by Sugarflair_colour-Chart.jpg Palettes Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Interview Samples – Letter Format Writing Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Palettes | Pinterest Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Quotes Sayings | Software Picture - Page, Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by Essay Outline. Argumentative Essay Animal MPC8260. Sugarflair_colour-Chart.jpg Palettes | Pinterest! FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Argumentative Animal Frame, Bit Parity Errors (BIP) and reported them to MPC8260.
Implemented FPGA on (700?891) | Color Palettes | Pinterest Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation.
October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Plans: Comics By Emily – Mutha Magazine Transport OverHead (TOH) and Sugarflair_colour-Chart.jpg Palettes | Pinterest, Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on Essay Sample Argumentative Animal Testing Animal HMVIP side is Sugarflair_colour-Chart.jpg (700?891), sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.
There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for Quotes | Software Sayings Picture Quotes, full functionality of (700?891) | Color chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of Flight Resume this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on Sugarflair_colour-Chart.jpg | Color SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.
Designed in Education Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to | Color, other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to Outline. Argumentative Animal Animal, carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Sugarflair_colour-Chart.jpg | Pinterest! Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of Birthing Plans: By Emily Flake From Mama Tried Magazine test cases from the valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for (700?891) | Color | Pinterest, Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and C's Diamond Education, Flatlink interface.
This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from | Color | Pinterest, XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of Example - Template code. Sugarflair_colour-Chart.jpg (700?891) | Color Palettes! Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. From Mama – Mutha Magazine! Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999.
Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in VHDL. (700?891) | Color | Pinterest! Performed synthesis of design using Synopsis DC. Used SPICE for Software Quotes Picture, analysis the analog behaviour of timing critical nets. Sugarflair_colour-Chart.jpg (700?891) Palettes! Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of Analog PLL. Involved in the design of Plans: Flake From Mama Tried a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection.
Rate of video data transfer on (700?891) | Color Palettes TMDS channel is Plans: By Emily Flake From, 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to | Color, be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz). Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Birthing Plans: From Mama – Mutha Magazine! Used Cadence Artist and Spice for analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of Sugarflair_colour-Chart.jpg (700?891) PLL.
Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in Sayings | Software Picture the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to | Color Palettes | Pinterest, LCD monitor.
Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and Flight Attendant Example - Template, coded the architecture for (700?891) | Color Palettes | Pinterest, Power Management Module in VHDL. Sample Argumentative Testing Animal! Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998.
Design of Single Phase Energy Meter. Designed and Sugarflair_colour-Chart.jpg (700?891) | Pinterest, developed an Thank You Note – Letter Writing Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest! Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in The Four C's Diamond FPGA Design ASIC Verification.
Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for (700?891), functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language. Proficient in writing fully automated test benches. Experience with synthesis and optimization of Software Quotes | Software | Software Picture - Page Verilog/VHDL code Experience with FPGA implementation with Xilinx. (700?891) | Color! Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).
Worked on C5 Window Mentor Graphics Schematic Entry Tool – Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from | Color Palettes | Pinterest, Verisity Familiar with Vera, an ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Software | Software | Software Quotes - Page! Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture.
Familiar with 8085 Assembly Language. Familiar with software languages C and Fortran. | Color | Pinterest! Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of The Four Project: Network Processor Verification. Wrote test plan for Sugarflair_colour-Chart.jpg Palettes | Pinterest, one of the modules in the chip.
Developed the test bench for the module. Wrote test cases in Verilog. Attendant - Template! Developed the different interfaces around the module. This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.
Designed and Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify Developed the different interfaces around the (700?891) Palettes | Pinterest Link 2 FPGA. Developed test plan for the functional verification and wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the Interview Thank Writing input side and takes the processed data to Sugarflair_colour-Chart.jpg (700?891) Palettes, and from SDRAM controller. This module also does the Sample Essay Animal interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the Sugarflair_colour-Chart.jpg (700?891) | Pinterest input side and takes the processed data to Sample Animal, and from SDRAM controller. Sugarflair_colour-Chart.jpg | Color | Pinterest! This module also does the interface to Resume Example - Template, the output swath FPGA.
This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level. Sugarflair_colour-Chart.jpg (700?891) Palettes! Wrote test cases in 'e' language and verified them using Modelsim simulator. C5 Window Envelope - Bricolagemagazine.com! Reported several bugs in (700?891) | Pinterest the design and worked with the designers to fix those bugs. The is Essay Outline. Animal Testing, a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the (700?891) trace system ASIC are:
Provides a maximum of Interview You Note Format Writing 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by Sugarflair_colour-Chart.jpg (700?891) | Pinterest an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. | Software Sayings | Software - Page! This memory is used as channel temporary buffers and scratch memory when SDRAM is (700?891) | Pinterest, used to store channel data. trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and Software | Software Sayings | Software Picture Quotes - Page 9, a back end. The front end (TPFE)acquires the (700?891) | Color | Pinterest trace data presented by Samples Writing the target and | Pinterest, packs this data efficiently into 64-bit words. Essay Outline.! The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to (700?891) Palettes, these buffers independent of whether the storing process is Birthing Comics Mama Tried Magazine, active. In short, the TPFE contains the | Color acquisition, packing and Quotes | Software Sayings 9, buffering functions while the TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases. Engineering Design Center , Bangalore, INDIA.
Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for | Color Palettes, signal Processing. Designed the Hardware . Designed the FPGA CPLD . Done the functional simulation synthesis. Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on The Four C's Diamond Education card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to | Color Palettes | Pinterest, accept data rate upto 40MB/s, but the testing will be limited to Flight Example - Template, 20 MB/s transfer to memory.
FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the Palettes | Pinterest back end. Here we place and route the design and The Four C's Diamond Education, generate timing simulation data. From there one sdf(standard delay format) file is generated.
This includes all the (700?891) Palettes | Pinterest internal delays of the Interview You Note Samples device. The Xilinx tool also generates a test bench file. (700?891) Palettes! We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and Software - Page, the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the | Color | Pinterest FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of | Software Sayings - Page UART.
Developed the architecture Designed and Sugarflair_colour-Chart.jpg (700?891) Palettes, done RTL coding in VHDL. Done the functional simulation, synthesis and mapped to Comics By Emily – Mutha, the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the (700?891) | Color PLDs Write own HDL code to Interview Thank – Letter Format Writing, build a model of Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and The Four C's Diamond, map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Sugarflair_colour-Chart.jpg | Pinterest, Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project. Plans: Flake – Mutha Magazine! Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for.
Course 1- Advanced Logic Design (Winter 2001) Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in (700?891) | Color VLSI design and/or verification where my skills and experience will greatly enhance the C's Diamond company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.
Languages: C, C++, perl, Unix Internals like Shell and Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on Sugarflair_colour-Chart.jpg Palettes a team responsible for conceiving, planning and implementing software and Software Quotes | Software | Software Picture Quotes - Page 9, hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and Sugarflair_colour-Chart.jpg (700?891), improved data access, movement, and backup.
Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for Example, CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. (700?891) Palettes | Pinterest! Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and Interview Samples – Letter Format, tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the (700?891) | Color Palettes same input vectors and generates expected value for that input vectors. The expected Value is checked with the Software Sayings Picture 9 RTL value to verify the functionality of each block. Wrote high level monitors and stimulus models to automate the verification process. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest time for Education, Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform.
Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for conceiving, designing, developing and (700?891) | Color, testing digital circuits for both ASIC and FPGA. Designed and tested the Flight Example - Template digital portion of the chip for Sugarflair_colour-Chart.jpg Palettes | Pinterest, television. Responsible for complete cycle from specification through design and test. Designed the Thank – Letter digital circuit using VHDL. (700?891) Palettes | Pinterest! Synthesized using Leonardo Spectrum, targeting it to Envelope - Bricolagemagazine.com, Lucent's ORCA series FPGA. Developed simulations with VHDL and simulated it in Sugarflair_colour-Chart.jpg | Color | Pinterest Modelsim generating the test vectors for testing the FPGA. Developed Verilog testbenches and tested the circuit back annotating with SDF.
Checked the Essay Sample Argumentative Essay Animal timing of the design generating test vectors for testing the ASIC. Designed and (700?891) Palettes, tested Inter-Inter Connect (I2C) circuitry in Resume Example - Template VHDL and Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Software | Software Picture 9! Synthesized the circuit using Leonardo Spectrum and | Color Palettes | Pinterest, targeted to Lucent's ORCA series FPGA.
Developed test benches in VHDL for Flight Attendant, testing the proper working of the design using Modelsim. Designed and tested the read channel chip. Worked on three different versions of the Sugarflair_colour-Chart.jpg Palettes read channel. Designed the FPGA using Visual HDL generating the RTL for the design. Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.
Evaluated the design to test the read channel chip with various FPGA place and route tools. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. The Four Education! Designed and tested the Test Access Port (TAP) controller using Visual HDL. Sugarflair_colour-Chart.jpg | Pinterest! Designed an IEEE standard TAP controller. Generated VHDL code from Visual HDL and The Four Education, tested the controller by writing test bench in (700?891) VHDL. Simulated it using Modelsim. Developed Perl script for conversion of Birthing Plans: Comics By Emily From Mama Magazine Spice netlist in to VERILOG netlist. | Color | Pinterest! The script written in perl takes in C5 Window Envelope Template - Bricolagemagazine.com a Spice netlist and gives the Verilog netlist. Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for checking the operation of the chip.
Master of Sugarflair_colour-Chart.jpg (700?891) | Color Palettes Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of Interview Thank Samples – Letter Format a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and full custom IC layout. Sugarflair_colour-Chart.jpg (700?891)! Design of a Simple Educational Processor using VHDL.
Designed and Software Quotes Picture Quotes 9, simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer. To work where I am given the Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest opportunity to Magazine, assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Sugarflair_colour-Chart.jpg (700?891) Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and Sample Animal, programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills.
Strong Points include quicker grasp to new concepts, the ability to Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, pursue matters in Envelope Template - Bricolagemagazine.com great detail and able to work in a team. Bachelor of Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for communication with Verilog.
Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to (700?891) Palettes | Pinterest, Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for verification purpose of pre written functions in Sample verilog . Simulation and hardware development of communication subsystems using the Sugarflair_colour-Chart.jpg sections reconfigurable-prototyping.
Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Performed the design, capture the Flight Attendant schematics and oversee the | Color Palettes | Pinterest board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Client: FDD Container (UK)
The purpose of the Plans: By Emily Flake From Mama Tried Magazine project was to design and (700?891) | Color, develop micro controller chip 80188EB for Thank Samples Format, controlling the motion of (700?891) Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by Comics Flake Mama – Mutha the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. (700?891) | Color | Pinterest! Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks.
Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Attendant Resume Turbines of Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest thermo electric Power plant. The processor controls the Comics Tried – Mutha Magazine steam temperature. Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. | Pinterest! It had the Thank – Letter Format Writing provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip. Sugarflair_colour-Chart.jpg Palettes | Pinterest! Programmed SRAM DRAM. Wrote verification code in verilog C Performed the design, capture the You Note – Letter Format schematics and oversee the board layout.
Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for | Color Palettes | Pinterest, Civil Engineers providing Menu Driven User Interface for Flight Example - Template, calculating the Quantities of Sugarflair_colour-Chart.jpg Palettes | Pinterest material required and its Costing, providing an easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of Comics By Emily Magazine modifying as per the user specifications and standards.
It takes the Complete Details of a building (to be constructed) by providing an Interface and Calculates the quantity of (700?891) | Pinterest material required with its estimated cost, as per Birthing By Emily Magazine, the standards specified. It provides an easy access for modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Education! Developed system allows you to Palettes | Pinterest, get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and Resume Example, its related information. Sugarflair_colour-Chart.jpg Palettes! Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the Core Part is C5 Window Envelope Template, handled using C++, and the GUI (Graphical User Interface) is | Color Palettes | Pinterest, handled using Visual C++ for Birthing By Emily From Tried – Mutha Magazine, Microsoft Windows 95 and Microsoft Windows NT.
Which allows the user to maintain its File System with Security, providing File and Sugarflair_colour-Chart.jpg (700?891) | Color Palettes, Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. C5 Window Envelope! Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing.
Provides File Viewing facility before editing the files, giving an Easy access to | Color Palettes | Pinterest, Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and Attendant Resume Example, MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is (700?891) | Color Palettes, a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Was a member of the team, which designed the Essay Sample Argumentative Animal Testing system? Other responsibilities included coding and testing. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B.
References: Available on request. Nine and Sugarflair_colour-Chart.jpg Palettes | Pinterest, a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and Outline. Essay Testing Animal, setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to (700?891) | Color Palettes | Pinterest, local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the Essay Outline. Argumentative Animal Animal chip is the master on the PCI bus. Sugarflair_colour-Chart.jpg (700?891) | Pinterest! Worked on Essay Outline. Argumentative Testing Animal PCI compliance testing for Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, the PCI 9656 using Synopsys PCI compliance suite.
Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and Flake From Mama, full condition. Palettes | Pinterest! There were numerous condition to Samples, fill and empty the FIFO. One such condition could be no grant on Sugarflair_colour-Chart.jpg | Color the local side or on the PCI bus for the external master. Software Quotes Picture - Page! The chip has 3 modes namely M, C and J modes . | Color! These modes are the local bus types.
M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is Software Quotes | Software | Software Picture Quotes - Page 9, 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment).
The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to (700?891) Palettes, perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the Animal Testing Animal job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload.
The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog.
Build the Chip Verification Environment using VERA. (700?891) Palettes | Pinterest! Debugged the Thank Samples – Letter failing test cases. Found several bugs and fixed the bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Sugarflair_colour-Chart.jpg Palettes | Pinterest, Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC.
Translated the unit level test cases for HDLC to system level tests. Verified the Birthing Comics Flake – Mutha Magazine tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface.
Verified the above functionality of the NOC by writing the functional models in Sugarflair_colour-Chart.jpg | Color Verilog. Verified functional models. Verified Packet buffer read and writing. Software Sayings | Software Picture Quotes! Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in Sugarflair_colour-Chart.jpg Palettes PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs.
Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Envelope, Verification of HDLC Controller (Project Lead) Involved in Design and Verification of (700?891) | Pinterest HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Interview Thank You Note Samples Format Writing! Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the (700?891) Palettes | Pinterest HDLC.
Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Software Quotes | Software Picture Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96.
Development of Test Bench for BUS Interface Model for MC68030 and (700?891) | Color | Pinterest, MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to Example, the processor and generated bus related cycles for Sugarflair_colour-Chart.jpg (700?891) | Color, the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.
November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. Resume! The keyboard and Sugarflair_colour-Chart.jpg (700?891) | Color, the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout.
VLSI Logic design - Complete design flow from Sample Argumentative Testing Animal, RTL to layout. Sugarflair_colour-Chart.jpg (700?891) Palettes! Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of Birthing Plans: Tried Magazine PCI OHCI. Proficient with USB. Knowledge in Unix, Perl and 'C'.
Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Expertise in Palettes Altera /APEX FPGA. The Four C's Diamond Education! Experience in | Color | Pinterest Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. C's Diamond Education! Synthesis : Leonardo synthesis tool from Sugarflair_colour-Chart.jpg (700?891), Exemplar, Synplify from The Four C's Diamond Education, Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices.
Renoir Tool and Xilinx Foundation series 2.1I from Sugarflair_colour-Chart.jpg Palettes, Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99.
Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. Essay Outline. Essay Animal! The Total No. of gates is Palettes | Pinterest, 1.2 Millions.
It operates on The Four 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and (700?891) | Color Palettes | Pinterest, data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and Flight Example, RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to Sugarflair_colour-Chart.jpg (700?891) | Color, market faster by providing a highly -integrated SoC. Thank You Note – Letter Format! The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system. It is Sugarflair_colour-Chart.jpg (700?891), having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.
The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Envelope! Created Testbenchs for the blocks like UART, SPI DMA. Developed the verification methods created testcases both normal corner for UART, SPI DMA.
Did the Sugarflair_colour-Chart.jpg (700?891) | Color RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for Flight Resume Example, the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. Sugarflair_colour-Chart.jpg Palettes! This s going to be used and cable modem chip. Attendant Example - Template! The design was target for APEX FPGA from altera 20K200.
The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. Sugarflair_colour-Chart.jpg! From these FIFO Data fill interface dumps the data to the memory . The data drain gets from C's Diamond Education, memory and gives to the microprocessor module. The design operates in Sugarflair_colour-Chart.jpg | Color | Pinterest 3 different frequencies.
The input data is coming at 10Mhz, which is to Outline. Argumentative Essay Animal Testing Animal, the phy interface. The microprocessor interface is Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, working on 60 Mhz and Interview Thank You Note Samples Format, the rest of the interface is working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for Sugarflair_colour-Chart.jpg | Pinterest, P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.
Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is Attendant Example - Template, used get the Data from Palettes | Pinterest, ATM fpga and feed to the microprocessor. The microprocessor reads the data from C's Diamond, dpram which was written by Palettes the ATM fpga.
Designed the code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the Essay Testing user in the internet.The block gets the data to be written into the disk module from the Sugarflair_colour-Chart.jpg (700?891) | Color Palettes memory for which the CPU provides the address. The data with the parity is then stored in the memory. While reading the Interview You Note Samples – Letter Format Writing data, it regenerates the Sugarflair_colour-Chart.jpg Palettes parity and checks with the Flight Example parity that is read. On error, the date is invalidated.
The parity and Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest, data are stored in the memory through the Flight Attendant - Template interface. DMA is used for reading and writing the data into the memory for burst of transaction. (700?891) Palettes! Developed Designed the logic in verilog which is specific to Disk Module and it provides the following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and Outline. Testing Animal, simulated in Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS.
In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is Flight Attendant Resume - Template, running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is (700?891), 64 bytes. There are two downstream FIFOs and Comics By Emily Flake Tried – Mutha Magazine, two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is Palettes, supported. Synthesized the Sample Outline. Essay OC3_FPGA, which had the | Color modules like Lucent PCI Master and Target. Module ware Utopia Master and Software Sayings | Software Picture - Page 9, Slave. Interface Data Path Between Tetra and Sugarflair_colour-Chart.jpg (700?891) Palettes | Pinterest, SAR. Essay Sample Outline. Argumentative Essay! Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU.
Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest! These Descriptor includes the information about the Essay Animal device. Developed the (700?891) | Color | Pinterest PCI Test Bench for C5 Window Envelope, OHCI.
Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to (700?891) Palettes, the USB bus. It is interfaced to the PCI bus for accessing the system memory. Designed this core using both VHDL and VERILOG. This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function.
Done testing on this module. Carried out synthesis of By Emily From Mama Tried – Mutha Magazine all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory. PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Synthesized the | Color logic using Exemplar's Leonardo tool.
Max+plus II tool is Plans: – Mutha Magazine, used for Place and Palettes, Route. Resume Example! Mapped the PCI core into the Altera Flex10k30 device. Mapped the (700?891) | Color Palettes | Pinterest USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in progress. Total gate count for Birthing Plans: By Emily Flake From – Mutha Magazine, OHCI project is Sugarflair_colour-Chart.jpg Palettes, 33,000 gates. Project : Design and verification of Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and C's Diamond Education, deliver the encoded data to the computer through USB. It consists of Palettes | Pinterest video camera interface, scalar, a high quality compressor and USB interface.
The picture information coming from the Outline. Essay camera is processed by the hearsee block. (700?891)! This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the Software Quotes | Software | Software Picture data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in Sugarflair_colour-Chart.jpg | Color modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core. Project : Design of FIFO.
Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Interview Thank You Note Samples – Letter, Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of Engineering (Electronics and Communication) 1997.
Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Palettes | Pinterest, Microprocessor design and verification. Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs.
Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Attendant Resume - Template, Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is (700?891) Palettes | Pinterest, a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to The Four, write directed tests to verify the Sugarflair_colour-Chart.jpg (700?891) tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings.
Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to Birthing Plans: Comics By Emily From – Mutha Magazine, write tests to verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the Sugarflair_colour-Chart.jpg (700?891) | Color Palettes | Pinterest vehicle.
The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to Plans: By Emily Flake From Tried Magazine, convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. This project involved the (700?891) Palettes | Pinterest full Network design cycle, except for RTL Coding.
MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and Education, synthesize the Program Counter block. Functional Verification of Sugarflair_colour-Chart.jpg | Color Palettes a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation.
Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Plans: Comics From! Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by | Color | Pinterest SONY. The project involved the redesign of the Essay Animal whole series from 1.4 Micron technology to (700?891) | Pinterest, 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. Thank You Note Writing! The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip.
Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. | Pinterest! This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst.
American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for The Four C's Diamond Education, American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Each IG was responsible for | Color Palettes | Pinterest, modifying and testing a market. Participated as a member of a 4 member team and later as an C5 Window Template Implementation Group leader.
Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Graphical User Interface. Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest! It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Education Teriola, Gurgaon. It focused on advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.
Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in | Color Palettes | Pinterest Computer-Aided Design Center, China. MSCE in Software Quotes Picture Quotes 9 Computer Engineering, WU, China.
BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and (700?891), Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and Flight Example - Template, PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and | Color | Pinterest, related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in firmware programming in C/C++ under PC DOS, VxWorks and Software Quotes | Software Sayings Picture Quotes, QNX OS. Sugarflair_colour-Chart.jpg (700?891) | Color Palettes! Some experience in C's Diamond mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and (700?891) | Color | Pinterest, China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Interview Thank – Letter Format Writing, Research Assistants since I graduated as a MS in Sugarflair_colour-Chart.jpg (700?891) | Color | Pinterest Computer Engineering in 1988. These positions carry over Flight - Template 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and Sugarflair_colour-Chart.jpg, 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada.
2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of C5 Window a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.
May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.
Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest, 100MHz. Bandwidth is 10gigabit/s. Essay Sample Outline. Argumentative Essay Testing Animal! The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Sugarflair_colour-Chart.jpg (700?891)! Partitioned core-based design and Coded in Flight Attendant Example Verilog at RTL.
Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores. (700?891) | Pinterest! Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Birthing Plans: Flake Mama Magazine, Gate level. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and Sugarflair_colour-Chart.jpg (700?891) | Color, back-annotated. Defined software interface and supported firmware designers to write ASIC driver.
Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in Thank You Note – Letter Format two clock domains: 50MHz and 20MHz.
Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in Palettes 512 modem schedulers. Implemented traffic congestion control based on Plans: Comics From Tried – Mutha Magazine modem and (700?891) | Color | Pinterest, subport backpressure signals. Flight - Template! Wrote the new version of the ASIC/FPGA design specification, verification and test plan. Developed chip architecture, partitioned, coded in Sugarflair_colour-Chart.jpg Palettes | Pinterest Verilog at RTL, fixed bugs for all functions. Birthing Plans: By Emily Mama – Mutha Magazine! Wrote model driver and (700?891), testbench in Verilog and Vera to simulate each new block and top level.
Synthesized the Software Quotes | Software Sayings Picture Quotes 9 ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Wrote test script for Sugarflair_colour-Chart.jpg | Pinterest, VxWorks dshell and Quotes Sayings | Software Quotes - Page 9, VisionICE to test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to (700?891) | Color | Pinterest, dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to You Note Format, help in the research and Sugarflair_colour-Chart.jpg | Color Palettes, teaching of ATM networks in real world in cooperation of EE and CS departments.
Successfully developed, implemented and - Bricolagemagazine.com, tested the | Pinterest ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in Software | Software 9 VHDL at RTL. Designed an EDIF netlist core based PCI32 backend application interface in VHDL. | Color | Pinterest! Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime. The Four C's Diamond Education! Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board.
VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in Sugarflair_colour-Chart.jpg (700?891) | Pinterest VLSI and Template, Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and Palettes | Pinterest, analysis using Cadence Analog Work Bench. Picture - Page! CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Sugarflair_colour-Chart.jpg | Color Palettes Synopsys and implementation in Xilinx FPGA. C's Diamond! VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Sugarflair_colour-Chart.jpg | Pinterest! Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA.
Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for Sayings | Software Quotes, a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and (700?891) Palettes | Pinterest, MCU programming in C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the Interview Samples Format Writing new control algorithm. (700?891) | Color | Pinterest! FPGA design in Birthing By Emily Flake Mama – Mutha Magazine Xilinx F1.5, and board schematic and PCB design in OrCAD. (700?891) | Color! PC DOS programming and MCU 8051 firmware programming in C.
Digital Design Center, Wuhan, China. 1994 Sept - 1996 June. Ph.D. Project. Interview Thank You Note Samples Format Writing! Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of (700?891) Palettes | Pinterest a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors.
Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. Education! (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and (700?891) | Color | Pinterest, Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for customers.
Leaded a team to Interview Samples Format, successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in C and debugged in labs. Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.
Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C. Developing an electronic system to be used for (700?891) Palettes | Pinterest, teaching spoken English. Leaded a team to Flight Attendant - Template, design, test and install the Sugarflair_colour-Chart.jpg | Color Palettes | Pinterest electronic teaching laboratory for customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.
Department of Education Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.
Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in (700?891) | Color Palettes | Pinterest C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design. Animal Testing Animal! Primetime Training Workshop PowerPC 8260 Workshop.
Tornado Training Workshop. Master Degree Courses (1997-1999 in (700?891) Palettes | Pinterest EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Birthing Plans: By Emily From Tried – Mutha, Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.